387fd3ca26
Add 3.18 support based on 3.18-rc6. Only netboot tested. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 43461
157 lines
5.7 KiB
Diff
157 lines
5.7 KiB
Diff
From 4bdfacdeaf3c988c4f3256c88118893eac640b03 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 8 Dec 2013 14:17:50 +0100
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Subject: [PATCH 52/53] MIPS: BCM63XX: split PCIE reset signals
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---
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arch/mips/bcm63xx/reset.c | 39 ++++++++++++++--------
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 2 ++
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arch/mips/pci/pci-bcm63xx.c | 7 ++++
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3 files changed, 34 insertions(+), 14 deletions(-)
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--- a/arch/mips/bcm63xx/reset.c
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+++ b/arch/mips/bcm63xx/reset.c
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@@ -28,7 +28,9 @@
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[BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \
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[BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \
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[BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
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- [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
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+ [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, \
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+ [BCM63XX_RESET_PCIE_CORE] = BCM## __cpu ##_RESET_PCIE_CORE, \
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+ [BCM63XX_RESET_PCIE_HARD] = BCM## __cpu ##_RESET_PCIE_HARD,
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#define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK
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#define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK
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@@ -42,6 +44,8 @@
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#define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK
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#define BCM3368_RESET_PCIE 0
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#define BCM3368_RESET_PCIE_EXT 0
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+#define BCM3368_RESET_PCIE_CORE 0
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+#define BCM3368_RESET_PCIE_HARD 0
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#define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK
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@@ -54,11 +58,10 @@
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#define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK
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#define BCM6318_RESET_PCM 0
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#define BCM6318_RESET_MPI 0
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-#define BCM6318_RESET_PCIE \
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- (SOFTRESET_6318_PCIE_MASK | \
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- SOFTRESET_6318_PCIE_CORE_MASK | \
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- SOFTRESET_6318_PCIE_HARD_MASK)
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+#define BCM6318_RESET_PCIE SOFTRESET_6318_PCIE_MASK
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#define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK
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+#define BCM6318_RESET_PCIE_CORE SOFTRESET_6318_PCIE_CORE_MASK
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+#define BCM6318_RESET_PCIE_HARD SOFTRESET_6318_PCIE_HARD_MASK
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#define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
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#define BCM6328_RESET_ENET 0
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@@ -70,11 +73,10 @@
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#define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK
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#define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK
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#define BCM6328_RESET_MPI 0
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-#define BCM6328_RESET_PCIE \
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- (SOFTRESET_6328_PCIE_MASK | \
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- SOFTRESET_6328_PCIE_CORE_MASK | \
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- SOFTRESET_6328_PCIE_HARD_MASK)
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+#define BCM6328_RESET_PCIE SOFTRESET_6328_PCIE_MASK
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#define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK
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+#define BCM6328_RESET_PCIE_CORE SOFTRESET_6328_PCIE_CORE_MASK
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+#define BCM6328_RESET_PCIE_HARD SOFTRESET_6328_PCIE_HARD_MASK
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#define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK
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#define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK
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@@ -88,6 +90,8 @@
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#define BCM6338_RESET_MPI 0
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#define BCM6338_RESET_PCIE 0
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#define BCM6338_RESET_PCIE_EXT 0
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+#define BCM6338_RESET_PCIE_CORE 0
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+#define BCM6338_RESET_PCIE_HARD 0
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#define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK
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#define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK
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@@ -101,6 +105,8 @@
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#define BCM6348_RESET_MPI 0
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#define BCM6348_RESET_PCIE 0
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#define BCM6348_RESET_PCIE_EXT 0
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+#define BCM6348_RESET_PCIE_CORE 0
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+#define BCM6348_RESET_PCIE_HARD 0
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#define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK
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#define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK
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@@ -114,6 +120,8 @@
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#define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK
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#define BCM6358_RESET_PCIE 0
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#define BCM6358_RESET_PCIE_EXT 0
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+#define BCM6358_RESET_PCIE_CORE 0
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+#define BCM6358_RESET_PCIE_HARD 0
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#define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK
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#define BCM6362_RESET_ENET 0
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@@ -125,9 +133,10 @@
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#define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK
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#define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK
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#define BCM6362_RESET_MPI 0
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-#define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \
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- SOFTRESET_6362_PCIE_CORE_MASK)
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+#define BCM6362_RESET_PCIE SOFTRESET_6362_PCIE_MASK
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#define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK
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+#define BCM6362_RESET_PCIE_CORE SOFTRESET_6362_PCIE_CORE_MASK
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+#define BCM6362_RESET_PCIE_HARD 0
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#define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
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#define BCM6368_RESET_ENET 0
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@@ -141,6 +150,8 @@
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#define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK
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#define BCM6368_RESET_PCIE 0
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#define BCM6368_RESET_PCIE_EXT 0
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+#define BCM6368_RESET_PCIE_CORE 0
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+#define BCM6368_RESET_PCIE_HARD 0
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#define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK
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#define BCM63268_RESET_ENET 0
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@@ -152,10 +163,10 @@
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#define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK
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#define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK
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#define BCM63268_RESET_MPI 0
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-#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \
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- SOFTRESET_63268_PCIE_CORE_MASK | \
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- SOFTRESET_63268_PCIE_HARD_MASK)
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+#define BCM63268_RESET_PCIE SOFTRESET_63268_PCIE_MASK
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#define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK
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+#define BCM63268_RESET_PCIE_CORE SOFTRESET_63268_PCIE_CORE_MASK
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+#define BCM63268_RESET_PCIE_HARD SOFTRESET_63268_PCIE_HARD_MASK
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/*
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* core reset bits
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
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@@ -14,6 +14,8 @@ enum bcm63xx_core_reset {
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BCM63XX_RESET_MPI,
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BCM63XX_RESET_PCIE,
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BCM63XX_RESET_PCIE_EXT,
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+ BCM63XX_RESET_PCIE_CORE,
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+ BCM63XX_RESET_PCIE_HARD,
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};
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void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
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--- a/arch/mips/pci/pci-bcm63xx.c
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+++ b/arch/mips/pci/pci-bcm63xx.c
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@@ -135,9 +135,16 @@ static void __init bcm63xx_reset_pcie(vo
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/* reset the PCIe core */
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bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1);
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bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
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+ if (BCMCPU_IS_6328() || BCMCPU_IS_63268()) {
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 1);
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+ mdelay(10);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0);
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+ }
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mdelay(10);
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+ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0);
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bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
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mdelay(10);
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