d523866eb3
These patches add support for ipq806x NAND flash controller. Most of these are cherry-picked & backported from LKML: *https://lkml.org/lkml/2015/8/3/16 This patch just modifies the kernel code, but doesn't change the config. It should be harmless. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46568
75 lines
2.1 KiB
Diff
75 lines
2.1 KiB
Diff
From 4c385b25fab119144bffb255ad77712fe586ac10 Mon Sep 17 00:00:00 2001
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From: Archit Taneja <architt@codeaurora.org>
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Date: Thu, 2 Apr 2015 11:20:41 +0530
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Subject: [PATCH] clk: qcom: Add EBI2 clocks for IPQ806x
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The NAND controller within EBI2 requires EBI2_CLK and
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EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so
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that they can be used by the NAND controller driver. Add an entry
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for EBI2_AON_CLK in the gcc-ipq806x DT binding document.
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Signed-off-by: Archit Taneja <architt@codeaurora.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/qcom/gcc-ipq806x.c | 32 ++++++++++++++++++++++++++++
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include/dt-bindings/clock/qcom,gcc-ipq806x.h | 1 +
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2 files changed, 33 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -2239,6 +2239,36 @@ static struct clk_branch usb_fs1_h_clk =
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},
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};
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+static struct clk_branch ebi2_clk = {
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+ .hwcg_reg = 0x3b00,
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+ .hwcg_bit = 6,
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+ .halt_reg = 0x2fcc,
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+ .halt_bit = 1,
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+ .clkr = {
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+ .enable_reg = 0x3b00,
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+ .enable_mask = BIT(4),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ebi2_clk",
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+ .ops = &clk_branch_ops,
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+ .flags = CLK_IS_ROOT,
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+ },
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+ },
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+};
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+
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+static struct clk_branch ebi2_aon_clk = {
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+ .halt_reg = 0x2fcc,
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+ .halt_bit = 0,
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+ .clkr = {
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+ .enable_reg = 0x3b00,
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+ .enable_mask = BIT(8),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "ebi2_always_on_clk",
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+ .ops = &clk_branch_ops,
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+ .flags = CLK_IS_ROOT,
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+ },
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+ },
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+};
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+
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static struct clk_regmap *gcc_ipq806x_clks[] = {
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[PLL0] = &pll0.clkr,
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[PLL0_VOTE] = &pll0_vote,
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@@ -2341,6 +2371,8 @@ static struct clk_regmap *gcc_ipq806x_cl
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[USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
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[USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
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[USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
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+ [EBI2_CLK] = &ebi2_clk.clkr,
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+ [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
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[PLL9] = &hfpll0.clkr,
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[PLL10] = &hfpll1.clkr,
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[PLL12] = &hfpll_l2.clkr,
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--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
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+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
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@@ -289,5 +289,6 @@
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#define UBI32_CORE2_CLK_SRC 278
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#define UBI32_CORE1_CLK 279
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#define UBI32_CORE2_CLK 280
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+#define EBI2_AON_CLK 281
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#endif
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