667f6c7f49
Manually rebased patches:
bcm27xx/patches-5.4/950-0135-spi-spi-bcm2835-Disable-forced-software-CS.patch
generic-backport/744-v5.5-net-sfp-soft-status-and-control-support.patch
layerscape/patches-5.4/819-uart-0005-tty-serial-fsl_lpuart-enable-dma-mode-for-imx8qxp.patch
mvebu/patches-5.4/521-arm64-dts-marvell-espressobin-Add-ethernet-switch-al.patch
Removed:
layerscape/patches-5.4/819-uart-0012-tty-serial-lpuart-add-LS1028A-support.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
lantiq/Easybox 904 xDSL, x86_64
Run-tested: ipq806x/R7800, lantiq/Easybox 904 xDSL, x86_64
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
Co-developed-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
55 lines
1.6 KiB
Diff
55 lines
1.6 KiB
Diff
From d2cf2f91ba5b6d7696b1870e28017a3e1a7a1bb8 Mon Sep 17 00:00:00 2001
|
|
From: Tim Harvey <tharvey@gateworks.com>
|
|
Date: Fri, 28 Feb 2020 11:46:07 -0800
|
|
Subject: [PATCH] ARM: dts: imx6qdl-gw5910: add CC1352 UART
|
|
|
|
The GW5910-C revision adds a TI CC1352 connected to IMX UART4
|
|
|
|
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
---
|
|
arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 25 +++++++++++++++++++++++++
|
|
1 file changed, 25 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
|
|
+++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
|
|
@@ -218,6 +218,14 @@
|
|
status = "okay";
|
|
};
|
|
|
|
+/* cc1352 */
|
|
+&uart3 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_uart3>;
|
|
+ uart-has-rtscts;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
/* Sterling-LWB Bluetooth */
|
|
&uart4 {
|
|
pinctrl-names = "default";
|
|
@@ -409,6 +417,23 @@
|
|
>;
|
|
};
|
|
|
|
+ pinctrl_uart3: uart3grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
|
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
|
+ MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
|
|
+ MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
|
|
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
|
|
+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
|
|
+ MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
|
|
+ MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
|
|
+ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
|
|
+ MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
|
|
+ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
|
|
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
|
|
+ >;
|
|
+ };
|
|
+
|
|
pinctrl_uart4: uart4grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
|