7d6cff4882
Changelog: * https://www.kernel.org/pub/linux/kernel/v3.x/ChangeLog-3.18.21 Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 46768
330 lines
8.7 KiB
Diff
330 lines
8.7 KiB
Diff
--- a/drivers/i2c/busses/Kconfig
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+++ b/drivers/i2c/busses/Kconfig
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@@ -715,6 +715,10 @@ config I2C_RALINK
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tristate "Ralink I2C Controller"
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select OF_I2C
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+config I2C_MT7621
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+ tristate "MT7621 I2C Controller"
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+ select OF_I2C
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+
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config HAVE_S3C2410_I2C
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bool
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help
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--- a/drivers/i2c/busses/Makefile
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+++ b/drivers/i2c/busses/Makefile
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@@ -67,6 +67,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
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obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
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obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
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obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
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+obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o
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obj-$(CONFIG_I2C_QUP) += i2c-qup.o
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obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
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obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
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--- /dev/null
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+++ b/drivers/i2c/busses/i2c-mt7621.c
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@@ -0,0 +1,303 @@
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+/*
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+ * drivers/i2c/busses/i2c-mt7621.c
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+ *
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+ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
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+ *
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+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
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+ * (C) 2014 Sittisak <sittisaks@hotmail.com>
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+ *
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+ * This software is licensed under the terms of the GNU General Public
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+ * License version 2, as published by the Free Software Foundation, and
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+ * may be copied, distributed, and modified under those terms.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ */
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+
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+#include <linux/interrupt.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/reset.h>
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+#include <linux/delay.h>
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+#include <linux/slab.h>
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+#include <linux/init.h>
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+#include <linux/errno.h>
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+#include <linux/platform_device.h>
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+#include <linux/i2c.h>
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+#include <linux/io.h>
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+#include <linux/err.h>
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+
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+#include <asm/mach-ralink/ralink_regs.h>
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+
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+#define REG_CONFIG_REG 0x00
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+#define REG_CLKDIV_REG 0x04
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+#define REG_DEVADDR_REG 0x08
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+#define REG_ADDR_REG 0x0C
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+#define REG_DATAOUT_REG 0x10
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+#define REG_DATAIN_REG 0x14
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+#define REG_STATUS_REG 0x18
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+#define REG_STARTXFR_REG 0x1C
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+#define REG_BYTECNT_REG 0x20
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+#define REG_SM0_IS_AUTOMODE 0x28
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+#define REG_SM0CTL0 0x40
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+
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+
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+#define I2C_STARTERR 0x10
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+#define I2C_ACKERR 0x08
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+#define I2C_DATARDY 0x04
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+#define I2C_SDOEMPTY 0x02
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+#define I2C_BUSY 0x01
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+
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+/* I2C_CFG register bit field */
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+#define I2C_CFG_ADDRLEN_8 (7<<5) /* 8 bits */
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+#define I2C_CFG_DEVADLEN_7 (6<<2)
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+#define I2C_CFG_ADDRDIS BIT(1)
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+#define I2C_CFG_DEVADDIS BIT(0)
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+
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+#define I2C_CFG_DEFAULT (I2C_CFG_ADDRLEN_8 | \
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+ I2C_CFG_DEVADLEN_7 | \
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+ I2C_CFG_ADDRDIS)
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+
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+#define I2C_RETRY 0x1000
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+
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+#define CLKDIV_VALUE 333
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+#define i2c_busy_loop (CLKDIV_VALUE*30)
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+
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+#define READ_CMD 0x01
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+#define WRITE_CMD 0x00
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+#define READ_BLOCK 16
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+
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+#define SM0_ODRAIN BIT(31)
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+#define SM0_VSYNC_MODE BIT(28)
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+#define SM0_CLK_DIV (CLKDIV_VALUE << 16)
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+#define SM0_WAIT_LEVEL BIT(6)
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+#define SM0_EN BIT(1)
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+
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+#define SM0_CFG_DEFUALT (SM0_ODRAIN | SM0_VSYNC_MODE | \
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+ SM0_CLK_DIV | SM0_WAIT_LEVEL | \
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+ SM0_EN)
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+/***********************************************************/
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+
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+static void __iomem *membase;
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+static struct i2c_adapter *adapter;
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+
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+static void rt_i2c_w32(u32 val, unsigned reg)
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+{
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+ iowrite32(val, membase + reg);
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+}
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+
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+static u32 rt_i2c_r32(unsigned reg)
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+{
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+ return ioread32(membase + reg);
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+}
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+
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+static void mt7621_i2c_reset(struct i2c_adapter *a)
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+{
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+ device_reset(a->dev.parent);
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+}
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+static void mt7621_i2c_enable(struct i2c_msg *msg)
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+{
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+ rt_i2c_w32(msg->addr,REG_DEVADDR_REG);
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+ rt_i2c_w32(0,REG_ADDR_REG);
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+}
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+
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+static void i2c_master_init(struct i2c_adapter *a)
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+{
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+ mt7621_i2c_reset(a);
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+ rt_i2c_w32(I2C_CFG_DEFAULT,REG_CONFIG_REG);
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+ rt_i2c_w32(SM0_CFG_DEFUALT,REG_SM0CTL0);
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+ rt_i2c_w32(1,REG_SM0_IS_AUTOMODE);//auto mode
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+}
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+
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+
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+static inline int rt_i2c_wait_rx_done(void)
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+{
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+ int i=0;
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+ while((!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY)) && (i<i2c_busy_loop))
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+ i++;
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+ if(i>=i2c_busy_loop){
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+ pr_err("err,wait for idle timeout");
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+ return -ETIMEDOUT;
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+ }
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+ return 0;
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+}
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+
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+static inline int rt_i2c_wait_idle(void)
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+{
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+ int i=0;
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+ while((rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY) && (i<i2c_busy_loop))
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+ i++;
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+ if(i>=i2c_busy_loop){
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+ pr_err("err,wait for idle timeout");
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+ return -ETIMEDOUT;
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+ }
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+ return 0;
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+}
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+
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+static inline int rt_i2c_wait_tx_done(void)
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+{
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+ int i=0;
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+ while((!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY)) && (i<i2c_busy_loop))
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+ i++;
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+ if(i>=i2c_busy_loop){
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+ pr_err("err,wait for idle timeout");
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+ return -ETIMEDOUT;
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+ }
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+ return 0;
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+}
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+
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+static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
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+{
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+ int i = 0, j = 0, pos = 0;
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+ int nblock = msg->len / READ_BLOCK;
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+ int rem = msg->len % READ_BLOCK;
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+
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+ if (msg->flags & I2C_M_TEN) {
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+ printk("10 bits addr not supported\n");
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+ return -EINVAL;
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+ }
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+
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+ if (msg->flags & I2C_M_RD) {
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+ for (i = 0; i < nblock; i++) {
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+ if (rt_i2c_wait_idle())
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+ goto err_timeout;
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+ rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
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+ rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
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+ for (j = 0; j < READ_BLOCK; j++) {
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+ if (rt_i2c_wait_rx_done())
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+ goto err_timeout;
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+ msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
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+ }
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+ }
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+
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+ if (rt_i2c_wait_idle())
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+ goto err_timeout;
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+ rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
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+ rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
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+
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+ for (i = 0; i < rem; i++) {
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+ if (rt_i2c_wait_rx_done())
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+ goto err_timeout;
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+ msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
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+ }
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+ } else {
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+ if (rt_i2c_wait_idle())
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+ goto err_timeout;
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+ rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
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+ for (i = 0; i < msg->len; i++) {
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+ rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
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+ if(i == 0)
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+ rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
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+
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+ if (rt_i2c_wait_tx_done())
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+ goto err_timeout;
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+ }
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+ }
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+
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+ return 0;
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+err_timeout:
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+ return -ETIMEDOUT;
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+}
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+
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+static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
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+{
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+ int i = 0;
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+ int ret = 0;
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+ i2c_master_init(a);
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+ mt7621_i2c_enable(m);
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+
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+ for (i = 0; i != n && ret==0; i++) {
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+ ret = rt_i2c_handle_msg(a, &m[i]);
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+ if (ret)
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+ return ret;
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+ }
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+ return i;
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+}
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+
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+static u32 rt_i2c_func(struct i2c_adapter *a)
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+{
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+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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+}
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+
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+static const struct i2c_algorithm rt_i2c_algo = {
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+ .master_xfer = rt_i2c_master_xfer,
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+ .functionality = rt_i2c_func,
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+};
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+
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+static int rt_i2c_probe(struct platform_device *pdev)
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+{
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+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ int ret;
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+
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+ adapter = devm_kzalloc(&pdev->dev,sizeof(struct i2c_adapter), GFP_KERNEL);
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+ if (!adapter) {
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+ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
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+ return -ENOMEM;
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+ }
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+ membase = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(membase))
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+ return PTR_ERR(membase);
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+
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+ strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
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+
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+ adapter->owner = THIS_MODULE;
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+ adapter->nr = pdev->id;
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+ adapter->timeout = HZ;
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+ adapter->algo = &rt_i2c_algo;
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+ adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
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+ adapter->dev.parent = &pdev->dev;
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+ adapter->dev.of_node = pdev->dev.of_node;
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+
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+ platform_set_drvdata(pdev, adapter);
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+
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+ ret = i2c_add_numbered_adapter(adapter);
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+ if (ret)
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+ return ret;
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+
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+ dev_info(&pdev->dev,"loaded");
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+
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+ return 0;
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+}
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+
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+static int rt_i2c_remove(struct platform_device *pdev)
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+{
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+ platform_set_drvdata(pdev, NULL);
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+ return 0;
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+}
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+
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+static const struct of_device_id i2c_rt_dt_ids[] = {
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+ { .compatible = "ralink,i2c-mt7621", },
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+ { /* sentinel */ }
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+};
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+
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+MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
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+
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+static struct platform_driver rt_i2c_driver = {
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+ .probe = rt_i2c_probe,
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+ .remove = rt_i2c_remove,
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+ .driver = {
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+ .owner = THIS_MODULE,
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+ .name = "i2c-mt7621",
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+ .of_match_table = i2c_rt_dt_ids,
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+ },
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+};
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+
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+static int __init i2c_rt_init (void)
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+{
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+ return platform_driver_register(&rt_i2c_driver);
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+}
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+
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+static void __exit i2c_rt_exit (void)
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+{
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+ platform_driver_unregister(&rt_i2c_driver);
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+}
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+module_init (i2c_rt_init);
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+module_exit (i2c_rt_exit);
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+
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+MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
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+MODULE_DESCRIPTION("MT7621 I2c host driver");
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+MODULE_LICENSE("GPL");
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+MODULE_ALIAS("platform:MT7621-I2C");
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