1866368a8a
LS1088A is an ARMv8 implementation combining eight ARM A53 processor cores. The LS1088ARDB is an evaluatoin platform that supports the LS1088A family SoCs. Features summary: - Eight 64-bit ARM v8 Cortex-A53 CPUs - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces - QUADSPI flash, 3 PCIe, 2 USB, 1 SD, 2 DUARTs etc Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
791 lines
18 KiB
Diff
791 lines
18 KiB
Diff
From cbacf87fa6fb262c98033405f15697798c3a9c5d Mon Sep 17 00:00:00 2001
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From: Zhao Qiang <qiang.zhao@nxp.com>
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Date: Sun, 9 Oct 2016 14:31:50 +0800
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Subject: [PATCH 135/141] arm64: Add DTS support for FSL's LS1088ARDB
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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---
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arch/arm64/boot/dts/freescale/Makefile | 1 +
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arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 203 ++++++++
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arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 557 +++++++++++++++++++++
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3 files changed, 761 insertions(+)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
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--- a/arch/arm64/boot/dts/freescale/Makefile
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+++ b/arch/arm64/boot/dts/freescale/Makefile
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@@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
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+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
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@@ -0,0 +1,203 @@
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+/*
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+ * Device Tree file for Freescale LS1088a RDB board
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+ *
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+ * Copyright (C) 2015, Freescale Semiconductor
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+/dts-v1/;
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+
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+#include "fsl-ls1088a.dtsi"
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+
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+/ {
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+ model = "Freescale Layerscape 1088a RDB Board";
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+ compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
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+};
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+
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+&esdhc {
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+ status = "okay";
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+};
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+
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+&ifc {
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+ status = "disabled";
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+};
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+
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+&ftm0 {
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+ pca9547@77 {
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+ compatible = "philips,pca9547";
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+ reg = <0x77>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ i2c@2 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x2>;
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+
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+ ina220@40 {
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+ compatible = "ti,ina220";
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+ reg = <0x40>;
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+ shunt-resistor = <1000>;
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+ };
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+ };
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+
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+ i2c@3 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x3>;
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+
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+ rtc@51 {
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+ compatible = "nxp,pcf2129";
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+ reg = <0x51>;
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+ /* IRQ10_B */
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+ interrupts = <0 150 0x4>;
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+ };
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+
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+ adt7461a@4c {
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+ compatible = "adt7461a";
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+ reg = <0x4c>;
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+ };
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+ };
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+ };
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+};
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+
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+&i2c1 {
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+ status = "disabled";
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+};
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+
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+&i2c2 {
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+ status = "disabled";
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+};
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+
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+&i2c3 {
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+ status = "disabled";
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+};
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+
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+&dspi {
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+ status = "disabled";
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+};
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+
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+&qspi {
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+ status = "okay";
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+ qflash0: s25fs512s@0 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ reg = <0>;
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+ };
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+
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+ qflash1: s25fs512s@1 {
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+ compatible = "spansion,m25p80";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ reg = <1>;
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+ };
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+};
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+
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+&sata0 {
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+ status = "okay";
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+};
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+
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+&usb0 {
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+ status = "okay";
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+};
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+
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+&usb1 {
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+ status = "okay";
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+};
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+
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+&serial0 {
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+ status = "okay";
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+};
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+
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+&serial1 {
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+ status = "okay";
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+};
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+
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+&emdio1 {
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+ /* Freescale F104 PHY1 */
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+ mdio1_phy1: emdio1_phy@1 {
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+ reg = <0x1c>;
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+ phy-connection-type = "qsgmii";
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+ };
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+ mdio1_phy2: emdio1_phy@2 {
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+ reg = <0x1d>;
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+ phy-connection-type = "qsgmii";
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+ };
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+ mdio1_phy3: emdio1_phy@3 {
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+ reg = <0x1e>;
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+ phy-connection-type = "qsgmii";
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+ };
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+ mdio1_phy4: emdio1_phy@4 {
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+ reg = <0x1f>;
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+ phy-connection-type = "qsgmii";
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+ };
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+ /* F104 PHY2 */
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+ mdio1_phy5: emdio1_phy@5 {
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+ reg = <0x0c>;
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+ phy-connection-type = "qsgmii";
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+ };
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+ mdio1_phy6: emdio1_phy@6 {
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+ reg = <0x0d>;
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+ phy-connection-type = "qsgmii";
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+ };
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+ mdio1_phy7: emdio1_phy@7 {
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+ reg = <0x0e>;
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+ phy-connection-type = "qsgmii";
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+ };
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+ mdio1_phy8: emdio1_phy@8 {
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+ reg = <0x0f>;
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+ phy-connection-type = "qsgmii";
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+ };
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+};
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+
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+&emdio2 {
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+ /* Aquantia AQR105 10G PHY */
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+ mdio2_phy1: emdio2_phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ reg = <0x0>;
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+ phy-connection-type = "xfi";
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+ };
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+};
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+
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+/* DPMAC connections to external PHYs
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+ * based on LS1088A RM RevC - $24.1.2 SerDes Options
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+ */
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+/* DPMAC1 is 10G SFP+, fixed link */
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+&dpmac2 {
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+ phy-handle = <&mdio2_phy1>;
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+};
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+&dpmac3 {
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+ phy-handle = <&mdio1_phy5>;
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+};
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+&dpmac4 {
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+ phy-handle = <&mdio1_phy6>;
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+};
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+&dpmac5 {
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+ phy-handle = <&mdio1_phy7>;
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+};
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+&dpmac6 {
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+ phy-handle = <&mdio1_phy8>;
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+};
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+&dpmac7 {
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+ phy-handle = <&mdio1_phy1>;
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+};
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+&dpmac8 {
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+ phy-handle = <&mdio1_phy2>;
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+};
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+&dpmac9 {
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+ phy-handle = <&mdio1_phy3>;
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+};
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+&dpmac10 {
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+ phy-handle = <&mdio1_phy4>;
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
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@@ -0,0 +1,557 @@
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+/*
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+ * Device Tree Include file for Freescale Layerscape-1088A family SoC.
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+ *
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+ * Copyright (C) 2015, Freescale Semiconductor
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+ *
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+ */
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+
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+/memreserve/ 0x80000000 0x00010000;
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+
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+/ {
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+ compatible = "fsl,ls1088a";
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+ interrupt-parent = <&gic>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ cpus {
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+ #address-cells = <2>;
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+ #size-cells = <0>;
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+
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+ /* We have 2 clusters having 4 Cortex-A57 cores each */
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+ cpu0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x0>;
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+ clocks = <&clockgen 1 0>;
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+ };
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+
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x1>;
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+ clocks = <&clockgen 1 0>;
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+ };
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+
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+ cpu2: cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x2>;
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+ clocks = <&clockgen 1 0>;
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+ };
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+
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+ cpu3: cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x3>;
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+ clocks = <&clockgen 1 0>;
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+ };
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+
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+ cpu4: cpu@100 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x100>;
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+ clocks = <&clockgen 1 1>;
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+ };
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+
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+ cpu5: cpu@101 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x101>;
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+ clocks = <&clockgen 1 1>;
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+ };
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+
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+ cpu6: cpu@102 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x102>;
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+ clocks = <&clockgen 1 1>;
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+ };
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+
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+ cpu7: cpu@103 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53";
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+ reg = <0x0 0x103>;
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+ clocks = <&clockgen 1 1>;
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+ };
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+ };
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+
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+ pmu {
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+ compatible = "arm,armv8-pmuv3";
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+ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
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+ };
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+
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+ gic: interrupt-controller@6000000 {
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+ compatible = "arm,gic-v3";
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+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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+ <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
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+ <0x0 0x0c0c0000 0 0x2000>, /* GICC */
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+ <0x0 0x0c0d0000 0 0x1000>, /* GICH */
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+ <0x0 0x0c0e0000 0 0x20000>; /* GICV */
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+ #interrupt-cells = <3>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ interrupt-controller;
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+ interrupts = <1 9 0x4>;
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+
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+ its: gic-its@6020000 {
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+ compatible = "arm,gic-v3-its";
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+ msi-controller;
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+ reg = <0x0 0x6020000 0 0x20000>;
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+ };
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+ };
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+
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+ sysclk: sysclk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <100000000>;
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+ clock-output-names = "sysclk";
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+ };
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+
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+ clockgen: clocking@1300000 {
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+ compatible = "fsl,ls2080a-clockgen", "fsl,ls1088a-clockgen";
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+ reg = <0 0x1300000 0 0xa0000>;
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+ #clock-cells = <2>;
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+ clocks = <&sysclk>;
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+ };
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+
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+ serial0: serial@21c0500 {
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+ device_type = "serial";
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+ compatible = "fsl,ns16550", "ns16550a";
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+ reg = <0x0 0x21c0500 0x0 0x100>;
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+ clocks = <&clockgen 4 3>;
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+ interrupts = <0 32 0x4>; /* Level high type */
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+ };
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+
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+ serial1: serial@21c0600 {
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+ device_type = "serial";
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+ compatible = "fsl,ns16550", "ns16550a";
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+ reg = <0x0 0x21c0600 0x0 0x100>;
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+ clocks = <&clockgen 4 3>;
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+ interrupts = <0 32 0x4>; /* Level high type */
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+ };
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+
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+ gpio0: gpio@2300000 {
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+ compatible = "fsl,qoriq-gpio";
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+ reg = <0x0 0x2300000 0x0 0x10000>;
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+ interrupts = <0 36 0x4>; /* Level high type */
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+ gpio-controller;
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+ little-endian;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gpio1: gpio@2310000 {
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+ compatible = "fsl,qoriq-gpio";
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+ reg = <0x0 0x2310000 0x0 0x10000>;
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+ interrupts = <0 36 0x4>; /* Level high type */
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+ gpio-controller;
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+ little-endian;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gpio2: gpio@2320000 {
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+ compatible = "fsl,qoriq-gpio";
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+ reg = <0x0 0x2320000 0x0 0x10000>;
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+ interrupts = <0 37 0x4>; /* Level high type */
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+ gpio-controller;
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+ little-endian;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ gpio3: gpio@2330000 {
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+ compatible = "fsl,qoriq-gpio";
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+ reg = <0x0 0x2330000 0x0 0x10000>;
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+ interrupts = <0 37 0x4>; /* Level high type */
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+ gpio-controller;
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+ little-endian;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+
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+ /* TODO: WRIOP (CCSR?) */
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+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
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+ compatible = "fsl,fman-memac-mdio";
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+ reg = <0x0 0x8B96000 0x0 0x1000>;
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+ device_type = "mdio";
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+ little-endian; /* force the driver in LE mode */
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+
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+ /* Not necessary on the QDS, but needed on the RDB */
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
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+ compatible = "fsl,fman-memac-mdio";
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+ reg = <0x0 0x8B97000 0x0 0x1000>;
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+ device_type = "mdio";
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+ little-endian; /* force the driver in LE mode */
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ ifc: ifc@2240000 {
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+ compatible = "fsl,ifc", "simple-bus";
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+ reg = <0x0 0x2240000 0x0 0x20000>;
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+ interrupts = <0 21 0x4>; /* Level high type */
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+ little-endian;
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+
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+ ranges = <0 0 0x5 0x80000000 0x08000000
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+ 2 0 0x5 0x30000000 0x00010000
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+ 3 0 0x5 0x20000000 0x00010000>;
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+ };
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+
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+ esdhc: esdhc@2140000 {
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+ compatible = "fsl,ls2080a-esdhc", "fsl,ls1088a-esdhc", "fsl,esdhc";
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+ reg = <0x0 0x2140000 0x0 0x10000>;
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+ interrupts = <0 28 0x4>; /* Level high type */
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+ clock-frequency = <0>;
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+ voltage-ranges = <1800 1800 3300 3300>;
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+ sdhci,auto-cmd12;
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+ little-endian;
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+ bus-width = <4>;
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+ };
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+
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+ ftm0: ftm0@2800000 {
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+ compatible = "fsl,ftm-alarm";
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+ reg = <0x0 0x2800000 0x0 0x10000>;
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+ interrupts = <0 44 4>;
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+ };
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+
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+ reset: reset@1E60000 {
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+ compatible = "fsl,ls-reset";
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+ reg = <0x0 0x1E60000 0x0 0x10000>;
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+ };
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+
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+ dspi: dspi@2100000 {
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+ compatible = "fsl,ls2085a-dspi", "fsl,ls1088a-dspi";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x0 0x2100000 0x0 0x10000>;
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+ interrupts = <0 26 0x4>; /* Level high type */
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+ clocks = <&clockgen 4 3>;
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+ clock-names = "dspi";
|
|
+ spi-num-chipselects = <5>;
|
|
+ bus-num = <0>;
|
|
+ };
|
|
+
|
|
+ i2c0: i2c@2000000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2000000 0x0 0x10000>;
|
|
+ interrupts = <0 34 0x4>; /* Level high type */
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ i2c1: i2c@2010000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2010000 0x0 0x10000>;
|
|
+ interrupts = <0 34 0x4>; /* Level high type */
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ i2c2: i2c@2020000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2020000 0x0 0x10000>;
|
|
+ interrupts = <0 35 0x4>; /* Level high type */
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ i2c3: i2c@2030000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2030000 0x0 0x10000>;
|
|
+ interrupts = <0 35 0x4>; /* Level high type */
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ qspi: quadspi@20c0000 {
|
|
+ compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x20c0000 0x0 0x10000>,
|
|
+ <0x0 0x20000000 0x0 0x10000000>;
|
|
+ reg-names = "QuadSPI", "QuadSPI-memory";
|
|
+ interrupts = <0 25 0x4>; /* Level high type */
|
|
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
+ clock-names = "qspi_en", "qspi";
|
|
+ };
|
|
+
|
|
+ pcie@3400000 {
|
|
+ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
|
+ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 108 0x4>; /* aer interrupt */
|
|
+ interrupt-names = "aer";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ num-lanes = <4>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
|
|
+ <0000 0 0 2 &gic 0 0 0 110 4>,
|
|
+ <0000 0 0 3 &gic 0 0 0 111 4>,
|
|
+ <0000 0 0 4 &gic 0 0 0 112 4>;
|
|
+ };
|
|
+ pcie@3500000 {
|
|
+ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
|
+ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 113 0x4>; /* aer interrupt */
|
|
+ interrupt-names = "aer";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ num-lanes = <4>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
|
|
+ <0000 0 0 2 &gic 0 0 0 115 4>,
|
|
+ <0000 0 0 3 &gic 0 0 0 116 4>,
|
|
+ <0000 0 0 4 &gic 0 0 0 117 4>;
|
|
+ };
|
|
+
|
|
+ pcie@3600000 {
|
|
+ compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
|
+ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 118 0x4>; /* aer interrupt */
|
|
+ interrupt-names = "aer";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ num-lanes = <8>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
|
|
+ <0000 0 0 2 &gic 0 0 0 120 4>,
|
|
+ <0000 0 0 3 &gic 0 0 0 121 4>,
|
|
+ <0000 0 0 4 &gic 0 0 0 122 4>;
|
|
+ };
|
|
+
|
|
+ sata0: sata@3200000 {
|
|
+ compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
|
|
+ reg = <0x0 0x3200000 0x0 0x10000>;
|
|
+ interrupts = <0 133 0x4>; /* Level high type */
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ usb0: usb3@3100000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0x3100000 0x0 0x10000>;
|
|
+ interrupts = <0 80 0x4>; /* Level high type */
|
|
+ dr_mode = "host";
|
|
+ configure-gfladj;
|
|
+ snps,dis_rxdet_inp3_quirk;
|
|
+ };
|
|
+
|
|
+ usb1: usb3@3110000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0x3110000 0x0 0x10000>;
|
|
+ interrupts = <0 81 0x4>; /* Level high type */
|
|
+ dr_mode = "host";
|
|
+ configure-gfladj;
|
|
+ snps,dis_rxdet_inp3_quirk;
|
|
+ };
|
|
+
|
|
+ smmu: iommu@5000000 {
|
|
+ compatible = "arm,mmu-500";
|
|
+ reg = <0 0x5000000 0 0x800000>;
|
|
+ #global-interrupts = <12>;
|
|
+ interrupts = <0 13 4>, /* global secure fault */
|
|
+ <0 14 4>, /* combined secure interrupt */
|
|
+ <0 15 4>, /* global non-secure fault */
|
|
+ <0 16 4>, /* combined non-secure interrupt */
|
|
+ /* performance counter interrupts 0-7 */
|
|
+ <0 211 4>,
|
|
+ <0 212 4>,
|
|
+ <0 213 4>,
|
|
+ <0 214 4>,
|
|
+ <0 215 4>,
|
|
+ <0 216 4>,
|
|
+ <0 217 4>,
|
|
+ <0 218 4>,
|
|
+ /* per context interrupt, 64 interrupts */
|
|
+ <0 146 4>,
|
|
+ <0 147 4>,
|
|
+ <0 148 4>,
|
|
+ <0 149 4>,
|
|
+ <0 150 4>,
|
|
+ <0 151 4>,
|
|
+ <0 152 4>,
|
|
+ <0 153 4>,
|
|
+ <0 154 4>,
|
|
+ <0 155 4>,
|
|
+ <0 156 4>,
|
|
+ <0 157 4>,
|
|
+ <0 158 4>,
|
|
+ <0 159 4>,
|
|
+ <0 160 4>,
|
|
+ <0 161 4>,
|
|
+ <0 162 4>,
|
|
+ <0 163 4>,
|
|
+ <0 164 4>,
|
|
+ <0 165 4>,
|
|
+ <0 166 4>,
|
|
+ <0 167 4>,
|
|
+ <0 168 4>,
|
|
+ <0 169 4>,
|
|
+ <0 170 4>,
|
|
+ <0 171 4>,
|
|
+ <0 172 4>,
|
|
+ <0 173 4>,
|
|
+ <0 174 4>,
|
|
+ <0 175 4>,
|
|
+ <0 176 4>,
|
|
+ <0 177 4>,
|
|
+ <0 178 4>,
|
|
+ <0 179 4>,
|
|
+ <0 180 4>,
|
|
+ <0 181 4>,
|
|
+ <0 182 4>,
|
|
+ <0 183 4>,
|
|
+ <0 184 4>,
|
|
+ <0 185 4>,
|
|
+ <0 186 4>,
|
|
+ <0 187 4>,
|
|
+ <0 188 4>,
|
|
+ <0 189 4>,
|
|
+ <0 190 4>,
|
|
+ <0 191 4>,
|
|
+ <0 192 4>,
|
|
+ <0 193 4>,
|
|
+ <0 194 4>,
|
|
+ <0 195 4>,
|
|
+ <0 196 4>,
|
|
+ <0 197 4>,
|
|
+ <0 198 4>,
|
|
+ <0 199 4>,
|
|
+ <0 200 4>,
|
|
+ <0 201 4>,
|
|
+ <0 202 4>,
|
|
+ <0 203 4>,
|
|
+ <0 204 4>,
|
|
+ <0 205 4>,
|
|
+ <0 206 4>,
|
|
+ <0 207 4>,
|
|
+ <0 208 4>,
|
|
+ <0 209 4>;
|
|
+ mmu-masters = <&fsl_mc 0x300 0>;
|
|
+ };
|
|
+
|
|
+ timer {
|
|
+ compatible = "arm,armv8-timer";
|
|
+ interrupts = <1 13 0x1>,/*Phy Secure PPI, edge triggered*/
|
|
+ <1 14 0x1>, /*Phy Non-Secure PPI, edge triggered*/
|
|
+ <1 11 0x1>, /*Virtual PPI, edge triggered */
|
|
+ <1 10 0x1>; /*Hypervisor PPI, edge triggered */
|
|
+ };
|
|
+
|
|
+ fsl_mc: fsl-mc@80c000000 {
|
|
+ compatible = "fsl,qoriq-mc";
|
|
+ #stream-id-cells = <2>;
|
|
+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
|
+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
|
+ msi-parent = <&its>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ /*
|
|
+ * Region type 0x0 - MC portals
|
|
+ * Region type 0x1 - QBMAN portals
|
|
+ */
|
|
+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
|
|
+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
|
|
+
|
|
+ dpmacs {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dpmac1: dpmac@1 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <1>;
|
|
+ };
|
|
+ dpmac2: dpmac@2 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <2>;
|
|
+ };
|
|
+ dpmac3: dpmac@3 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <3>;
|
|
+ };
|
|
+ dpmac4: dpmac@4 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <4>;
|
|
+ };
|
|
+ dpmac5: dpmac@5 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <5>;
|
|
+ };
|
|
+ dpmac6: dpmac@6 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <6>;
|
|
+ };
|
|
+ dpmac7: dpmac@7 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <7>;
|
|
+ };
|
|
+ dpmac8: dpmac@8 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <8>;
|
|
+ };
|
|
+ dpmac9: dpmac@9 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <9>;
|
|
+ };
|
|
+ dpmac10: dpmac@10 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <0xa>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+
|
|
+ memory@80000000 {
|
|
+ device_type = "memory";
|
|
+ reg = <0x00000000 0x80000000 0 0x80000000>;
|
|
+ /* DRAM space 1 - 2 GB DRAM */
|
|
+ };
|
|
+};
|