c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
110 lines
4.0 KiB
Diff
110 lines
4.0 KiB
Diff
From 892a427f8a2b25b561298941cf1fc0373a98b269 Mon Sep 17 00:00:00 2001
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From: Jisheng Zhang <jszhang@marvell.com>
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Date: Wed, 16 Mar 2016 19:40:33 +0800
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Subject: [PATCH 58/70] PCI: designware: Move Root Complex setup code to
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dw_pcie_setup_rc()
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dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates
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IRQ domains, and enumerates devices below the bridge. dw_pcie_setup_rc()
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programs the Root Complex registers. The Root Complex may lose power
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during suspend-to-RAM, and when we resume, we want to redo the latter but
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not the former.
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Move some Root Complex programming from dw_pcie_host_init() to
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dw_pcie_setup_rc() where it belongs. DesignWare-based drivers can call
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dw_pcie_setup_rc() in their resume paths.
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[Niklas Cassel <niklas.cassel@axis.com>: This change moves outbound ATU
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programming, which uses pp->mem_base, to dw_pcie_setup_rc(). Apply the
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dra7xx pp->mem_base update before calling dw_pcie_setup_rc().]
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[bhelgaas: changelog, fold in dra7xx fix from Niklas]
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Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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---
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drivers/pci/host/pci-dra7xx.c | 4 ++--
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drivers/pci/host/pcie-designware.c | 39 ++++++++++++++++++------------------
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2 files changed, 21 insertions(+), 22 deletions(-)
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--- a/drivers/pci/host/pci-dra7xx.c
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+++ b/drivers/pci/host/pci-dra7xx.c
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@@ -142,13 +142,13 @@ static void dra7xx_pcie_enable_interrupt
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static void dra7xx_pcie_host_init(struct pcie_port *pp)
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{
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- dw_pcie_setup_rc(pp);
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-
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pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
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pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
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+ dw_pcie_setup_rc(pp);
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+
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dra7xx_pcie_establish_link(pp);
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if (IS_ENABLED(CONFIG_PCI_MSI))
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dw_pcie_msi_init(pp);
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -434,7 +434,6 @@ int dw_pcie_host_init(struct pcie_port *
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struct platform_device *pdev = to_platform_device(pp->dev);
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struct pci_bus *bus, *child;
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struct resource *cfg_res;
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- u32 val;
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int i, ret;
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LIST_HEAD(res);
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struct resource_entry *win;
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@@ -544,25 +543,6 @@ int dw_pcie_host_init(struct pcie_port *
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if (pp->ops->host_init)
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pp->ops->host_init(pp);
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- /*
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- * If the platform provides ->rd_other_conf, it means the platform
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- * uses its own address translation component rather than ATU, so
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- * we should not program the ATU here.
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- */
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- if (!pp->ops->rd_other_conf)
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- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
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- PCIE_ATU_TYPE_MEM, pp->mem_base,
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- pp->mem_bus_addr, pp->mem_size);
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-
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- dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
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-
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- /* program correct class for RC */
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- dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
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-
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- dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
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- val |= PORT_LOGIC_SPEED_CHANGE;
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- dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
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-
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pp->root_bus_nr = pp->busn->start;
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
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@@ -800,6 +780,25 @@ void dw_pcie_setup_rc(struct pcie_port *
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val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
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dw_pcie_writel_rc(pp, val, PCI_COMMAND);
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+
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+ /*
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+ * If the platform provides ->rd_other_conf, it means the platform
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+ * uses its own address translation component rather than ATU, so
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+ * we should not program the ATU here.
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+ */
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+ if (!pp->ops->rd_other_conf)
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+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
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+ PCIE_ATU_TYPE_MEM, pp->mem_base,
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+ pp->mem_bus_addr, pp->mem_size);
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+
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+ dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
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+
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+ /* program correct class for RC */
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+ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
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+
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+ dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
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+ val |= PORT_LOGIC_SPEED_CHANGE;
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+ dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
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}
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MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
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