cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
91 lines
3.3 KiB
Diff
91 lines
3.3 KiB
Diff
From 1693e5693b77f0d172aac8adcfaa4888d64f8996 Mon Sep 17 00:00:00 2001
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From: Marc Kleine-Budde <mkl@pengutronix.de>
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Date: Fri, 1 Mar 2019 13:54:19 +0100
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Subject: [PATCH] can: flexcan: introduce struct flexcan_priv::tx_mask and make
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use of it
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The current driver uses FLEXCAN_IFLAG2_MB() to generate the mask to check for
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the TX complete interrupt. This works well, as the driver will always use the
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last mailbox for TX, which falls into the iflag2 register.
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To support CANFD the payload size has to increase to 64 bytes and the
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number of mailboxes will decrease so much that the TX mailbox will be
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handled in the iflag1 register.
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This patch introduces a tx_mask in the struct flexcan_priv (similar to rx_mask)
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and makes use of it. The actual support to handle the TX mailbox in iflag1 will
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be added in the next patches.
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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---
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drivers/net/can/flexcan.c | 14 ++++++++------
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1 file changed, 8 insertions(+), 6 deletions(-)
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--- a/drivers/net/can/flexcan.c
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+++ b/drivers/net/can/flexcan.c
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@@ -143,7 +143,6 @@
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#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
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#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
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#define FLEXCAN_IFLAG_MB(x) BIT_ULL(x)
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-#define FLEXCAN_IFLAG2_MB(x) BIT((x) & 0x1f)
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#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
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#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
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#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
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@@ -279,6 +278,7 @@ struct flexcan_priv {
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u8 clk_src; /* clock source of CAN Protocol Engine */
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u64 rx_mask;
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+ u64 tx_mask;
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u32 reg_ctrl_default;
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struct clk *clk_ipg;
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@@ -891,7 +891,8 @@ static irqreturn_t flexcan_irq(int irq,
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struct flexcan_priv *priv = netdev_priv(dev);
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struct flexcan_regs __iomem *regs = priv->regs;
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irqreturn_t handled = IRQ_NONE;
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- u32 reg_iflag2, reg_esr;
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+ u64 reg_iflag_tx;
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+ u32 reg_esr;
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enum can_state last_state = priv->can.state;
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/* reception interrupt */
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@@ -925,10 +926,10 @@ static irqreturn_t flexcan_irq(int irq,
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}
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}
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- reg_iflag2 = priv->read(®s->iflag2);
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+ reg_iflag_tx = (u64)priv->read(®s->iflag2) << 32;
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/* transmission complete interrupt */
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- if (reg_iflag2 & FLEXCAN_IFLAG2_MB(priv->tx_mb_idx)) {
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+ if (reg_iflag_tx & priv->tx_mask) {
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u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
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handled = IRQ_HANDLED;
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@@ -940,7 +941,7 @@ static irqreturn_t flexcan_irq(int irq,
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/* after sending a RTR frame MB is in RX mode */
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priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
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&priv->tx_mb->can_ctrl);
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- priv->write(FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), ®s->iflag2);
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+ priv->write(priv->tx_mask >> 32, ®s->iflag2);
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netif_wake_queue(dev);
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}
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@@ -1227,7 +1228,7 @@ static int flexcan_chip_start(struct net
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/* enable interrupts atomically */
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disable_irq(dev->irq);
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priv->write(priv->reg_ctrl_default, ®s->ctrl);
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- reg_imask = priv->rx_mask | FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
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+ reg_imask = priv->rx_mask | priv->tx_mask;
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priv->write(upper_32_bits(reg_imask), ®s->imask2);
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priv->write(lower_32_bits(reg_imask), ®s->imask1);
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enable_irq(dev->irq);
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@@ -1297,6 +1298,7 @@ static int flexcan_open(struct net_devic
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flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
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priv->tx_mb_idx = priv->mb_count - 1;
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priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
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+ priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
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priv->offload.mailbox_read = flexcan_mailbox_read;
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