Openwrt/target/linux/layerscape/patches-5.4/302-dts-0064-arm64-dts-lx2160a-update-interrupt-property-for-Aqua.patch
Yangbo Lu cddd459140 layerscape: add patches-5.4
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release
which was tagged LSDK-20.04-V5.4.
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in
LSDK, port the dts patches from 4.14.

The patches are sorted into the following categories:
  301-arch-xxxx
  302-dts-xxxx
  303-core-xxxx
  701-net-xxxx
  801-audio-xxxx
  802-can-xxxx
  803-clock-xxxx
  804-crypto-xxxx
  805-display-xxxx
  806-dma-xxxx
  807-gpio-xxxx
  808-i2c-xxxx
  809-jailhouse-xxxx
  810-keys-xxxx
  811-kvm-xxxx
  812-pcie-xxxx
  813-pm-xxxx
  814-qe-xxxx
  815-sata-xxxx
  816-sdhc-xxxx
  817-spi-xxxx
  818-thermal-xxxx
  819-uart-xxxx
  820-usb-xxxx
  821-vfio-xxxx

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-05-07 12:53:06 +02:00

32 lines
1.1 KiB
Diff

From e463f4a9d933d2d62a065bba356a9eb04a9f3ac0 Mon Sep 17 00:00:00 2001
From: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Date: Tue, 11 Jun 2019 23:53:45 +0300
Subject: [PATCH] arm64: dts: lx2160a: update interrupt property for Aquantia
phy
Update Aquantia AQR107 nodes interrupt property.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -200,13 +200,13 @@
aquantia_phy1: ethernet-phy@4 {
/* AQR107 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-ieee802.3-c45";
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x4>;
};
aquantia_phy2: ethernet-phy@5 {
/* AQR107 PHY - "compatible" property not strictly needed */
compatible = "ethernet-phy-ieee802.3-c45";
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5>;
};
};