Openwrt/target/linux/ath79/dts/ar9330.dtsi
Adrian Schmutzler dc1280ef65 ath79: enable gpio on ar933x by default
All other SoC DTSI files have gpio enabled by default, only
ar9330/ar9331 disable it by default, only to have it enabled again
afterwards for each individual device.

So, do not disable it in the first place, and drop all device-specific
status statements afterwards.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2020-07-03 17:37:02 +02:00

214 lines
3.7 KiB
Plaintext

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/clock/ath79-clk.h>
#include "ath79.dtsi"
/ {
compatible = "qca,ar9330";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mips,mips24Kc";
clocks = <&pll ATH79_CLK_CPU>;
reg = <0>;
};
};
chosen {
bootargs = "console=ttyATH0,115200";
};
ahb {
apb {
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar7240-ddr-controller";
reg = <0x18000000 0x100>;
#qca,ddr-wb-channel-cells = <1>;
};
uart: uart@18020000 {
compatible = "qca,ar9330-uart";
reg = <0x18020000 0x14>;
interrupts = <3>;
clocks = <&pll ATH79_CLK_REF>;
clock-names = "uart";
status = "disabled";
};
gpio: gpio@18040000 {
compatible = "qca,ar7100-gpio";
reg = <0x18040000 0x34>;
interrupts = <2>;
ngpios = <30>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pinmux: pinmux@18040028 {
compatible = "pinctrl-single";
reg = <0x18040028 0x8>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x1>;
#pinctrl-cells = <2>;
jtag_disable_pins: pinmux_jtag_disable_pins {
pinctrl-single,bits = <0x0 0x1 0x1>;
};
switch_led_disable_pins: pinmux_switch_led_disable_pins {
pinctrl-single,bits = <0x0 0x0 0xf8>;
};
};
pll: pll-controller@18050000 {
compatible = "qca,ar9330-pll";
reg = <0x18050000 0x100>;
#clock-cells = <1>;
};
wdt: wdt@18060008 {
compatible = "qca,ar7130-wdt";
reg = <0x18060008 0x8>;
interrupts = <4>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "wdt";
};
rst: reset-controller@1806001c {
compatible = "qca,ar7100-reset";
reg = <0x1806001c 0x4>;
#reset-cells = <1>;
};
};
usb: usb@1b000000 {
compatible = "chipidea,usb2";
reg = <0x1b000000 0x200>;
interrupts = <3>;
resets = <&rst 5>;
reset-names = "usb-host";
phy-names = "usb-phy";
phys = <&usb_phy>;
status = "disabled";
};
spi: spi@1f000000 {
compatible = "qca,ar934x-spi";
reg = <0x1f000000 0x1c>;
clocks = <&pll ATH79_CLK_AHB>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gmac: gmac@18070000 {
compatible = "qca,ar9330-gmac";
reg = <0x18070000 0x4>;
};
wmac: wmac@18100000 {
compatible = "qca,ar9330-wmac";
reg = <0x18100000 0x20000>;
interrupts = <2>;
status = "disabled";
};
};
usb_phy: usb-phy {
compatible = "qca,ar7200-usb-phy";
reset-names = "usb-phy", "usb-suspend-override";
resets = <&rst 4>, <&rst 3>;
#phy-cells = <0>;
status = "disabled";
};
};
&cpuintc {
qca,ddr-wb-channel-interrupts = <2>, <3>;
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
};
&eth0 {
compatible = "qca,ar9330-eth", "syscon";
pll-data = <0x00110000 0x00001099 0x00991099>;
resets = <&rst 9>;
reset-names = "mac";
phy-handle = <&swphy4>;
};
&mdio1 {
status = "okay";
compatible = "qca,ar9330-mdio";
resets = <&rst 23>;
reset-names = "mdio";
builtin-switch;
builtin_switch: switch0@1f {
compatible = "qca,ar7240sw";
reg = <0x1f>;
resets = <&rst 8>;
reset-names = "switch";
qca,mib-poll-interval = <500>;
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
swphy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "mii";
};
};
};
};
&eth1 {
compatible = "qca,ar9330-eth", "syscon";
pll-data = <0x00110000 0x00001099 0x00991099>;
phy-mode = "gmii";
resets = <&rst 13>;
reset-names = "mac";
fixed-link {
speed = <1000>;
full-duplex;
};
};