cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
89 lines
3.4 KiB
Diff
89 lines
3.4 KiB
Diff
From bae75b5a56bc2c8768541b4b61edb28609486357 Mon Sep 17 00:00:00 2001
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From: Robin Gong <yibin.gong@nxp.com>
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Date: Tue, 4 Jul 2017 14:45:25 +0800
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Subject: [PATCH] MLK-15330-1: dma: fsl-edma-v3: combine two cells into one
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For dual fifo case, fsl-edma-v3 need add another cell. It's not friendly
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for user and it's possible other cells maybe added to other use cases,
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so combine two cells into one now, and for some special use cases such as
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dual fifo property can directly be passed by one bit of cell3 rather than
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another cell.
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Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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(cherry picked from commit 3ecd1b3382e2c746728842fb2c084fbb030eb5de)
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---
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Documentation/devicetree/bindings/dma/fsl-edma-v3.txt | 13 +++++++------
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drivers/dma/fsl-edma-v3.c | 9 ++++++---
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2 files changed, 13 insertions(+), 9 deletions(-)
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--- a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
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+++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
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@@ -14,12 +14,13 @@ Required properties:
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- interrupts : A list of interrupt-specifiers, each channel has one interrupt.
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- interrupt-names : Should contain:
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"edma-chan12-tx" - the channel12 transmission interrupt
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-- #dma-cells : Must be <4>.
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+- #dma-cells : Must be <3>.
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The 1st cell specifies the channel ID.
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The 2nd cell specifies the channel priority.
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- The 3rd cell specifies the channel type like for transmit or receive:
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+ The 3rd cell specifies the channel attributes which include below:
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+ BIT(0): transmit or receive:
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0: transmit, 1: receive.
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- The 4th cell specifies the local access or remote access:
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+ BIT(1): local or remote access:
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0: local, 1: remote.
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See the SoC's reference manual for all the supported request sources.
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- dma-channels : Number of channels supported by the controller
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@@ -31,7 +32,7 @@ edma0: dma-controller@40018000 {
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<0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
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<0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
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<0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
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- #dma-cells = <4>;
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+ #dma-cells = <3>;
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dma-channels = <4>;
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interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
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@@ -60,7 +61,7 @@ lpuart1: serial@5a070000 {
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assigned-clock-rates = <80000000>;
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power-domains = <&pd_dma_lpuart1>;
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dma-names = "tx","rx";
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- dmas = <&edma0 15 0 0 0>,
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- <&edma0 14 0 1 0>;
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+ dmas = <&edma0 15 0 0>,
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+ <&edma0 14 0 1>;
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status = "disabled";
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};
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--- a/drivers/dma/fsl-edma-v3.c
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+++ b/drivers/dma/fsl-edma-v3.c
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@@ -100,6 +100,9 @@
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_16_BYTES))
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+#define ARGS_RX BIT(0)
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+#define ARGS_REMOTE BIT(1)
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+
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struct fsl_edma3_hw_tcd {
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__le32 saddr;
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__le16 soff;
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@@ -696,7 +699,7 @@ static struct dma_chan *fsl_edma3_xlate(
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struct dma_chan *chan, *_chan;
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struct fsl_edma3_chan *fsl_chan;
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- if (dma_spec->args_count != 4)
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+ if (dma_spec->args_count != 3)
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return NULL;
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mutex_lock(&fsl_edma3->fsl_edma3_mutex);
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@@ -710,8 +713,8 @@ static struct dma_chan *fsl_edma3_xlate(
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chan = dma_get_slave_channel(chan);
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chan->device->privatecnt++;
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fsl_chan->priority = dma_spec->args[1];
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- fsl_chan->is_rxchan = dma_spec->args[2];
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- fsl_chan->is_remote = dma_spec->args[3];
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+ fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
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+ fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
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mutex_unlock(&fsl_edma3->fsl_edma3_mutex);
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return chan;
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}
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