cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
72 lines
2.7 KiB
Diff
72 lines
2.7 KiB
Diff
From 916df9ddac295df428a304fd03ed492ad10e900c Mon Sep 17 00:00:00 2001
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From: Marc Kleine-Budde <mkl@pengutronix.de>
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Date: Fri, 1 Mar 2019 10:22:26 +0100
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Subject: [PATCH] can: flexcan: remove TX mailbox bit from struct
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flexcan_priv::rx_mask{1,2}
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The flexcan IP core has up to 64 mailboxes, each one has a corresponding
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interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
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imask1 or imask2 registers.
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In the timestamp (i.e. non FIFO) mode the driver needs to mask out all
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non RX interrupt sources and uses the precomputed values rx_mask1 and
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rx_mask2 of struct flexcan_priv for this.
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Currently these values cannot be used directly, as they contain the TX
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mailbox flag. This patch removes the TX flag from flexcan_priv::rx_mask1
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and flexcan_priv::rx_mask2, and sets the TX flag directly when writing
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the regs->iflag1 and regs->iflag2 into the hardware.
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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---
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drivers/net/can/flexcan.c | 14 +++++---------
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1 file changed, 5 insertions(+), 9 deletions(-)
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--- a/drivers/net/can/flexcan.c
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+++ b/drivers/net/can/flexcan.c
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@@ -879,8 +879,7 @@ static inline u64 flexcan_read_reg_iflag
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struct flexcan_regs __iomem *regs = priv->regs;
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u32 iflag1, iflag2;
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- iflag2 = priv->read(®s->iflag2) & priv->rx_mask2 &
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- ~FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
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+ iflag2 = priv->read(®s->iflag2) & priv->rx_mask2;
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iflag1 = priv->read(®s->iflag1) & priv->rx_mask1;
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return (u64)iflag2 << 32 | iflag1;
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@@ -1229,7 +1228,7 @@ static int flexcan_chip_start(struct net
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disable_irq(dev->irq);
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priv->write(priv->reg_ctrl_default, ®s->ctrl);
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priv->write(priv->rx_mask1, ®s->imask1);
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- priv->write(priv->rx_mask2, ®s->imask2);
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+ priv->write(priv->rx_mask2 | FLEXCAN_IFLAG2_MB(priv->tx_mb_idx), ®s->imask2);
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enable_irq(dev->irq);
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/* print chip status */
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@@ -1298,9 +1297,6 @@ static int flexcan_open(struct net_devic
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priv->tx_mb_idx = priv->mb_count - 1;
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priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
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- priv->rx_mask1 = 0;
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- priv->rx_mask2 = FLEXCAN_IFLAG2_MB(priv->tx_mb_idx);
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-
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priv->offload.mailbox_read = flexcan_mailbox_read;
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if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
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@@ -1311,12 +1307,12 @@ static int flexcan_open(struct net_devic
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imask = GENMASK_ULL(priv->offload.mb_last,
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priv->offload.mb_first);
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- priv->rx_mask1 |= imask;
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- priv->rx_mask2 |= imask >> 32;
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+ priv->rx_mask1 = imask;
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+ priv->rx_mask2 = imask >> 32;
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err = can_rx_offload_add_timestamp(dev, &priv->offload);
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} else {
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- priv->rx_mask1 |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
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+ priv->rx_mask1 = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
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FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
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err = can_rx_offload_add_fifo(dev, &priv->offload,
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FLEXCAN_NAPI_WEIGHT);
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