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Openwrt/target/linux/ipq806x/files-5.4/arch/arm/boot/dts/qcom-ipq8064.dtsi
Adrian Schmutzler ed761344d2 ipq806x: disentangle and clean up SoC DTSI files 
So far, the DTSI files on ipq806x had a linear inheritance:

  qcom-ipq8064.dtsi
  v
  qcom-ipq8064-v1.0.dtsi
  v
  qcom-ipq8064-v2.0.dtsi
  v
  qcom-ipq8065.dtsi

This poses problems when one wants to set something that is specific
to an architecture closer to the top of the tree.

In this patch, we remove the chain-like inheritance and have all
other files derived from qcom-ipq8064.dtsi (changing this name to
something more generic is not possible due to upstream use).

The removal of inheritance will require a few entries to be copied
from qcom-ipq8064-v2.0.dtsi to qcom-ipq8065.dtsi. However, it also
opens an opportunity for some clean-up:

- Many definitions can be improved by just using the innermost labels.

- Instead of disabling the CPU_SPC node for ipq8065, it is now off by
  default and enabled where needed.

- Instead of patching phy-tx0-term-offset into qcom-ipq8064.dtsi and
  then having it changed for qcom-ipq8064-v2.0/qcom-ipq8065, just have
  the appropriate settings done in the lower DTSI files directly.

- For the opp_table0 adjustments for ipq8065, just redefine what's
  changed, but don't add all the untouched properties again.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2020-07-06 16:21:15 +02:00

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/dts-v1/;
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm IPQ8064";
compatible = "qcom,ipq8064";
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
memory { device_type = "memory"; reg = <0 0>; };
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
qcom,acc = <&acpu0_aux>;
qcom,saw = <&saw0>;
clocks = <&kraitcc 0>, <&kraitcc 4>;
clock-names = "cpu", "l2";
clock-latency = <100000>;
cpu-supply = <&smb208_s2a>;
operating-points-v2 = <&opp_table0>;
voltage-tolerance = <5>;
cooling-min-state = <0>;
cooling-max-state = <10>;
#cooling-cells = <2>;
cpu-idle-states = <&CPU_SPC>;
};
cpu1: cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
qcom,acc = <&acpu1_aux>;
qcom,saw = <&saw1>;
clocks = <&kraitcc 1>, <&kraitcc 4>;
clock-names = "cpu", "l2";
clock-latency = <100000>;
cpu-supply = <&smb208_s2b>;
operating-points-v2 = <&opp_table0>;
voltage-tolerance = <5>;
cooling-min-state = <0>;
cooling-max-state = <10>;
#cooling-cells = <2>;
cpu-idle-states = <&CPU_SPC>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
qcom,saw = <&saw_l2>;
};
qcom,l2 {
qcom,l2-rates = <384000000 1000000000 1200000000>;
qcom,l2-cpufreq = <384000000 600000000 1200000000>;
qcom,l2-volt = <1100000 1100000 1150000>;
qcom,l2-supply = <&smb208_s1a>;
};
idle-states {
CPU_SPC: spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
status = "disabled";
entry-latency-us = <400>;
exit-latency-us = <900>;
min-residency-us = <3000>;
};
};
};
opp_table0: opp_table0 {
compatible = "operating-points-v2-qcom-cpu";
nvmem-cells = <&speedbin_efuse>;
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
opp-microvolt-speed0-pvs0-v0 = <1000000>;
opp-microvolt-speed0-pvs1-v0 = <925000>;
opp-microvolt-speed0-pvs2-v0 = <875000>;
opp-microvolt-speed0-pvs3-v0 = <800000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <100000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt-speed0-pvs0-v0 = <1050000>;
opp-microvolt-speed0-pvs1-v0 = <975000>;
opp-microvolt-speed0-pvs2-v0 = <925000>;
opp-microvolt-speed0-pvs3-v0 = <850000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <100000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt-speed0-pvs0-v0 = <1100000>;
opp-microvolt-speed0-pvs1-v0 = <1025000>;
opp-microvolt-speed0-pvs2-v0 = <995000>;
opp-microvolt-speed0-pvs3-v0 = <900000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <100000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt-speed0-pvs0-v0 = <1150000>;
opp-microvolt-speed0-pvs1-v0 = <1075000>;
opp-microvolt-speed0-pvs2-v0 = <1025000>;
opp-microvolt-speed0-pvs3-v0 = <950000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <100000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt-speed0-pvs0-v0 = <1200000>;
opp-microvolt-speed0-pvs1-v0 = <1125000>;
opp-microvolt-speed0-pvs2-v0 = <1075000>;
opp-microvolt-speed0-pvs3-v0 = <1000000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <100000>;
};
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt-speed0-pvs0-v0 = <1250000>;
opp-microvolt-speed0-pvs1-v0 = <1175000>;
opp-microvolt-speed0-pvs2-v0 = <1125000>;
opp-microvolt-speed0-pvs3-v0 = <1050000>;
opp-supported-hw = <0x1>;
clock-latency-ns = <100000>;
};
};
thermal-zones {
tsens_tz_sensor0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 0>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
tsens_tz_sensor1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 1>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
tsens_tz_sensor2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 2>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
tsens_tz_sensor3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 3>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
tsens_tz_sensor4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 4>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
tsens_tz_sensor5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 5>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
tsens_tz_sensor6 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 6>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
tsens_tz_sensor7 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 7>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
tsens_tz_sensor8 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 8>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
tsens_tz_sensor9 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 9>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
tsens_tz_sensor10 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&tsens 10>;
trips {
cpu-critical-hi {
temperature = <125000>;
hysteresis = <2000>;
type = "critical_high";
};
cpu-config-hi {
temperature = <105000>;
hysteresis = <2000>;
type = "configurable_hi";
};
cpu-config-lo {
temperature = <95000>;
hysteresis = <2000>;
type = "configurable_lo";
};
cpu-critical-low {
temperature = <0>;
hysteresis = <2000>;
type = "critical_low";
};
};
};
};
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
nss@40000000 {
reg = <0x40000000 0x1000000>;
no-map;
};
smem: smem@41000000 {
reg = <0x41000000 0x200000>;
no-map;
};
};
clocks {
cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
pxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
};
fab-scaling {
compatible = "qcom,fab-scaling";
clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
clock-names = "apps-fab-clk", "ddr-fab-clk";
fab_freq_high = <533000000>;
fab_freq_nominal = <400000000>;
cpu_freq_threshold = <1000000000>;
};
firmware {
scm {
compatible = "qcom,scm-ipq806x";
};
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
lpass@28100000 {
compatible = "qcom,lpass-cpu";
status = "disabled";
clocks = <&lcc AHBIX_CLK>,
<&lcc MI2S_OSR_CLK>,
<&lcc MI2S_BIT_CLK>;
clock-names = "ahbix-clk",
"mi2s-osr-clk",
"mi2s-bit-clk";
interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "lpass-irq-lpaif";
reg = <0x28100000 0x10000>;
reg-names = "lpass-lpaif";
};
qfprom: qfprom@700000 {
compatible = "qcom,qfprom", "syscon";
reg = <0x700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
tsens_calib: calib@400 {
reg = <0x400 0xb>;
};
tsens_backup: backup@410 {
reg = <0x410 0xb>;
};
speedbin_efuse: speedbin@0c0 {
reg = <0x0c0 0x4>;
};
};
rpm: rpm@108000 {
compatible = "qcom,rpm-ipq8064";
reg = <0x108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ack",
"err",
"wakeup";
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
clock-names = "ram";
#address-cells = <1>;
#size-cells = <0>;
rpmcc: clock-controller {
compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
#clock-cells = <1>;
};
regulators {
compatible = "qcom,rpm-smb208-regulators";
smb208_s1a: s1a {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s1b: s1b {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s2a: s2a {
regulator-min-microvolt = < 800000>;
regulator-max-microvolt = <1250000>;
qcom,switch-mode-frequency = <1200000>;
};
smb208_s2b: s2b {
regulator-min-microvolt = < 800000>;
regulator-max-microvolt = <1250000>;
qcom,switch-mode-frequency = <1200000>;
};
};
};
rng@1a500000 {
compatible = "qcom,prng";
reg = <0x1a500000 0x200>;
clocks = <&gcc PRNG_CLK>;
clock-names = "core";
};
qcom_pinmux: pinmux@800000 {
compatible = "qcom,ipq8064-pinctrl";
reg = <0x800000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
pcie0_pins: pcie0_pinmux {
mux {
pins = "gpio3";
function = "pcie1_rst";
drive-strength = <12>;
bias-disable;
};
};
pcie1_pins: pcie1_pinmux {
mux {
pins = "gpio48";
function = "pcie2_rst";
drive-strength = <12>;
bias-disable;
};
};
pcie2_pins: pcie2_pinmux {
mux {
pins = "gpio63";
function = "pcie3_rst";
drive-strength = <12>;
bias-disable;
output-low;
};
};
i2c4_pins: i2c4_pinmux {
mux {
pins = "gpio12", "gpio13";
function = "gsbi4";
drive-strength = <12>;
bias-disable;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
drive-strength = <10>;
bias-none;
};
};
nand_pins: nand_pins {
disable {
pins = "gpio34", "gpio35", "gpio36",
"gpio37", "gpio38";
function = "nand";
drive-strength = <10>;
bias-disable;
};
pullups {
pins = "gpio39";
function = "nand";
drive-strength = <10>;
bias-pull-up;
};
hold {
pins = "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45",
"gpio46", "gpio47";
function = "nand";
drive-strength = <10>;
bias-bus-hold;
};
};
mdio0_pins: mdio0_pins {
mux {
pins = "gpio0", "gpio1";
function = "mdio";
drive-strength = <8>;
bias-disable;
};
};
rgmii2_pins: rgmii2_pins {
mux {
pins = "gpio27", "gpio28", "gpio29",
"gpio30", "gpio31", "gpio32",
"gpio51", "gpio52", "gpio59",
"gpio60", "gpio61", "gpio62";
function = "rgmii2";
drive-strength = <8>;
bias-disable;
};
};
leds_pins: leds_pins {
mux {
pins = "gpio7", "gpio8", "gpio9",
"gpio26", "gpio53";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
output-low;
};
};
buttons_pins: buttons_pins {
mux {
pins = "gpio54";
drive-strength = <2>;
bias-pull-up;
};
};
};
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x02000000 0x1000>,
<0x02002000 0x1000>;
};
timer@200a000 {
compatible = "qcom,kpss-timer", "qcom,msm-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
clock-frequency = <25000000>,
<32768>;
clocks = <&sleep_clk>;
clock-names = "sleep";
cpu-offset = <0x80000>;
};
acpu0_aux: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
clock-output-names = "acpu0_aux";
};
acpu1_aux: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
clock-output-names = "acpu1_aux";
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
clock-output-names = "acpu_l2_aux";
};
kraitcc: clock-controller {
compatible = "qcom,krait-cc-v1";
#clock-cells = <1>;
};
saw0: regulator@2089000 {
compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
saw1: regulator@2099000 {
compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
saw_l2: regulator@02012000 {
compatible = "qcom,saw2", "syscon";
reg = <0x02012000 0x1000>;
regulator;
};
sic_non_secure: sic-non-secure@12100000 {
compatible = "syscon";
reg = <0x12100000 0x10000>;
};
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
reg = <0x12480000 0x100>;
clocks = <&gcc GSBI2_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
syscon-tcsr = <&tcsr>;
uart2: serial@12490000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12490000 0x1000>,
<0x12480000 0x1000>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
gsbi4: gsbi@16300000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <4>;
reg = <0x16300000 0x100>;
clocks = <&gcc GSBI4_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
syscon-tcsr = <&tcsr>;
gsbi4_serial: serial@16340000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16340000 0x1000>,
<0x16300000 0x1000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
i2c@16380000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16380000 0x1000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
gsbi5: gsbi@1a200000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <5>;
reg = <0x1a200000 0x100>;
clocks = <&gcc GSBI5_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
syscon-tcsr = <&tcsr>;
uart5: serial@1a240000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x1000>,
<0x1a200000 0x1000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
i2c@1a280000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi@1a280000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
gsbi7: gsbi@16600000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";
cell-index = <7>;
reg = <0x16600000 0x100>;
clocks = <&gcc GSBI7_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
syscon-tcsr = <&tcsr>;
gsbi7_serial: serial@16640000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16640000 0x1000>,
<0x16600000 0x1000>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
};
sata_phy: sata-phy@1b400000 {
compatible = "qcom,ipq806x-sata-phy";
reg = <0x1b400000 0x200>;
clocks = <&gcc SATA_PHY_CFG_CLK>;
clock-names = "cfg";
#phy-cells = <0>;
status = "disabled";
};
sata: sata@29000000 {
compatible = "qcom,ipq806x-ahci", "generic-ahci";
reg = <0x29000000 0x180>;
ports-implemented = <0x1>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SFAB_SATA_S_H_CLK>,
<&gcc SATA_H_CLK>,
<&gcc SATA_A_CLK>,
<&gcc SATA_RXOOB_CLK>,
<&gcc SATA_PMALIVE_CLK>;
clock-names = "slave_face", "iface", "core",
"rxoob", "pmalive";
assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
assigned-clock-rates = <100000000>, <100000000>;
phys = <&sata_phy>;
phy-names = "sata-phy";
status = "disabled";
};
qcom,ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x00500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
};
gcc: clock-controller@900000 {
compatible = "qcom,gcc-ipq8064";
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
tsens: thermal-sensor@900000 {
compatible = "qcom,ipq8064-tsens";
reg = <0x900000 0x3680>;
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
nvmem-cell-names = "calib", "calib_backup";
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <1>;
};
tcsr: syscon@1a400000 {
compatible = "qcom,tcsr-ipq8064", "syscon";
reg = <0x1a400000 0x100>;
};
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
sfpb_mutex_block: syscon@1200600 {
compatible = "syscon";
reg = <0x01200600 0x100>;
};
hs_phy_0: hs_phy_0 {
compatible = "qcom,dwc3-hs-usb-phy";
regmap = <&usb3_0>;
clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
};
ss_phy_0: ss_phy_0 {
compatible = "qcom,dwc3-ss-usb-phy";
regmap = <&usb3_0>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
};
usb3_0: usb3@110f8800 {
compatible = "qcom,dwc3", "syscon";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x110f8800 0x8000>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "core";
ranges;
resets = <&gcc USB30_0_MASTER_RESET>;
reset-names = "master";
status = "disabled";
dwc3_0: dwc3@11000000 {
compatible = "snps,dwc3";
reg = <0x11000000 0xcd00>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hs_phy_0>, <&ss_phy_0>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
snps,dis_u3_susphy_quirk;
};
};
hs_phy_1: hs_phy_1 {
compatible = "qcom,dwc3-hs-usb-phy";
regmap = <&usb3_1>;
clocks = <&gcc USB30_1_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
};
ss_phy_1: ss_phy_1 {
compatible = "qcom,dwc3-ss-usb-phy";
regmap = <&usb3_1>;
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
};
usb3_1: usb3@100f8800 {
compatible = "qcom,dwc3", "syscon";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x100f8800 0x8000>;
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "core";
ranges;
resets = <&gcc USB30_1_MASTER_RESET>;
reset-names = "master";
status = "disabled";
dwc3_1: dwc3@10000000 {
compatible = "snps,dwc3";
reg = <0x10000000 0xcd00>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hs_phy_1>, <&ss_phy_1>;
phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host";
snps,dis_u3_susphy_quirk;
};
};
pcie0: pci@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
0x1b502000 0x80
0x1b600000 0x100
0x0ff00000 0x100000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc PCIE_A_CLK>,
<&gcc PCIE_H_CLK>,
<&gcc PCIE_PHY_CLK>,
<&gcc PCIE_AUX_CLK>,
<&gcc PCIE_ALT_REF_CLK>;
clock-names = "core", "iface", "phy", "aux", "ref";
assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
assigned-clock-rates = <100000000>;
resets = <&gcc PCIE_ACLK_RESET>,
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
<&gcc PCIE_PCI_RESET>,
<&gcc PCIE_PHY_RESET>,
<&gcc PCIE_EXT_RESET>;
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
status = "disabled";
};
pcie1: pci@1b700000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b700000 0x1000
0x1b702000 0x80
0x1b800000 0x100
0x31f00000 0x100000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc PCIE_1_A_CLK>,
<&gcc PCIE_1_H_CLK>,
<&gcc PCIE_1_PHY_CLK>,
<&gcc PCIE_1_AUX_CLK>,
<&gcc PCIE_1_ALT_REF_CLK>;
clock-names = "core", "iface", "phy", "aux", "ref";
assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
assigned-clock-rates = <100000000>;
resets = <&gcc PCIE_1_ACLK_RESET>,
<&gcc PCIE_1_HCLK_RESET>,
<&gcc PCIE_1_POR_RESET>,
<&gcc PCIE_1_PCI_RESET>,
<&gcc PCIE_1_PHY_RESET>,
<&gcc PCIE_1_EXT_RESET>;
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
status = "disabled";
};
pcie2: pci@1b900000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b900000 0x1000
0x1b902000 0x80
0x1ba00000 0x100
0x35f00000 0x100000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <2>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc PCIE_2_A_CLK>,
<&gcc PCIE_2_H_CLK>,
<&gcc PCIE_2_PHY_CLK>,
<&gcc PCIE_2_AUX_CLK>,
<&gcc PCIE_2_ALT_REF_CLK>;
clock-names = "core", "iface", "phy", "aux", "ref";
assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
assigned-clock-rates = <100000000>;
resets = <&gcc PCIE_2_ACLK_RESET>,
<&gcc PCIE_2_HCLK_RESET>,
<&gcc PCIE_2_POR_RESET>,
<&gcc PCIE_2_PCI_RESET>,
<&gcc PCIE_2_PHY_RESET>,
<&gcc PCIE_2_EXT_RESET>;
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
pinctrl-0 = <&pcie2_pins>;
pinctrl-names = "default";
perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
status = "disabled";
};
adm_dma: dma@18300000 {
compatible = "qcom,adm";
reg = <0x18300000 0x100000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
clock-names = "core", "iface";
resets = <&gcc ADM0_RESET>,
<&gcc ADM0_PBUS_RESET>,
<&gcc ADM0_C0_RESET>,
<&gcc ADM0_C1_RESET>,
<&gcc ADM0_C2_RESET>;
reset-names = "clk", "pbus", "c0", "c1", "c2";
qcom,ee = <0>;
status = "disabled";
};
nand_controller: nand-controller@1ac00000 {
compatible = "qcom,ipq806x-nand";
reg = <0x1ac00000 0x800>;
clocks = <&gcc EBI2_CLK>,
<&gcc EBI2_AON_CLK>;
clock-names = "core", "aon";
dmas = <&adm_dma 3>;
dma-names = "rxtx";
qcom,cmd-crci = <15>;
qcom,data-crci = <3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
nss_common: syscon@03000000 {
compatible = "syscon";
reg = <0x03000000 0x0000FFFF>;
};
qsgmii_csr: syscon@1bb00000 {
compatible = "syscon";
reg = <0x1bb00000 0x000001FF>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <7>;
snps,rd_osr_lmt = <7>;
snps,blen = <16 0 0 0 0 0 0>;
};
mdio0: mdio@37000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,ipq8064-mdio", "syscon";
reg = <0x37000000 0x200000>;
resets = <&gcc GMAC_CORE1_RESET>;
reset-names = "stmmaceth";
clocks = <&gcc GMAC_CORE1_CLK>;
clock-names = "stmmaceth";
status = "disabled";
};
gmac0: ethernet@37000000 {
device_type = "network";
compatible = "qcom,ipq806x-gmac";
reg = <0x37000000 0x200000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,axi-config = <&stmmac_axi_setup>;
snps,pbl = <32>;
snps,aal = <1>;
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
clocks = <&gcc GMAC_CORE1_CLK>;
clock-names = "stmmaceth";
resets = <&gcc GMAC_CORE1_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
gmac1: ethernet@37200000 {
device_type = "network";
compatible = "qcom,ipq806x-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,axi-config = <&stmmac_axi_setup>;
snps,pbl = <32>;
snps,aal = <1>;
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
clocks = <&gcc GMAC_CORE2_CLK>;
clock-names = "stmmaceth";
resets = <&gcc GMAC_CORE2_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
gmac2: ethernet@37400000 {
device_type = "network";
compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,axi-config = <&stmmac_axi_setup>;
snps,pbl = <32>;
snps,aal = <1>;
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
clocks = <&gcc GMAC_CORE3_CLK>;
clock-names = "stmmaceth";
resets = <&gcc GMAC_CORE3_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
gmac3: ethernet@37600000 {
device_type = "network";
compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37600000 0x200000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,axi-config = <&stmmac_axi_setup>;
snps,pbl = <32>;
snps,aal = <1>;
qcom,nss-common = <&nss_common>;
qcom,qsgmii-csr = <&qsgmii_csr>;
clocks = <&gcc GMAC_CORE4_CLK>;
clock-names = "stmmaceth";
resets = <&gcc GMAC_CORE4_RESET>;
reset-names = "stmmaceth";
status = "disabled";
};
/* Temporary fixed regulator */
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sdcc1bam: dma@12402000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x8000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
sdcc3bam: dma@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
amba: amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
sdcc1: sdcc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
vmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
dma-names = "tx", "rx";
};
sdcc3: sdcc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x12180000 0x2000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <192000000>;
#mmc-ddr-1_8v;
sd-uhs-sdr104;
sd-uhs-ddr50;
vqmmc-supply = <&vsdcc_fixed>;
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
dma-names = "tx", "rx";
};
};
};
sfpb_mutex: sfpb-mutex {
compatible = "qcom,sfpb-mutex";
syscon = <&sfpb_mutex_block 4 4>;
#hwlock-cells = <1>;
};
smem {
compatible = "qcom,smem";
memory-region = <&smem>;
hwlocks = <&sfpb_mutex 3>;
};
};
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