f0f35fdac1
This reverts commit d7f21940bc.
Winbond W25Q256FV and W25Q256JV both uses 0xef4019 as JEDEC ID,
but only the latter has proper 4B_OPCODES support.
W25Q256FV has all 4B read instructions but it lacks a 4B page program
instruction, causing the entire flash to be read-only.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
80 lines
2.8 KiB
Diff
80 lines
2.8 KiB
Diff
From: Felix Fietkau <nbd@nbd.name>
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Date: Sat, 4 Nov 2017 07:40:23 +0100
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Subject: [PATCH] mtd: spi-nor: support limiting 4K sectors support based on
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flash size
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Some devices need 4K sectors to be able to deal with small flash chips.
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For instance, w25x05 is 64 KiB in size, and without 4K sectors, the
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entire chip is just one erase block.
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On bigger flash chip sizes, using 4K sectors can significantly slow down
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many operations, including using a writable filesystem. There are several
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platforms where it makes sense to use a single kernel on both kinds of
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devices.
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To support this properly, allow configuring an upper flash chip size
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limit for 4K sectors support.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/drivers/mtd/spi-nor/Kconfig
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+++ b/drivers/mtd/spi-nor/Kconfig
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@@ -34,6 +34,17 @@ config SPI_ASPEED_SMC
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and support for the SPI flash memory controller (SPI) for
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the host firmware. The implementation only supports SPI NOR.
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+config MTD_SPI_NOR_USE_4K_SECTORS_LIMIT
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+ int "Maximum flash chip size to use 4K sectors on (in KiB)"
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+ depends on MTD_SPI_NOR_USE_4K_SECTORS
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+ default "4096"
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+ help
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+ There are many flash chips that support 4K sectors, but are so large
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+ that using them significantly slows down writing large amounts of
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+ data or using a writable filesystem.
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+ Any flash chip larger than the size specified in this option will
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+ not use 4K sectors.
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+
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config SPI_CADENCE_QUADSPI
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tristate "Cadence Quad SPI controller"
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depends on OF && (ARM || ARM64 || COMPILE_TEST)
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -4464,6 +4464,7 @@ static void spi_nor_info_init_params(str
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struct spi_nor_erase_map *map = ¶ms->erase_map;
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const struct flash_info *info = nor->info;
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struct device_node *np = spi_nor_get_flash_node(nor);
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+ struct mtd_info *mtd = &nor->mtd;
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u8 i, erase_mask;
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/* Initialize legacy flash parameters and settings. */
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@@ -4527,6 +4528,21 @@ static void spi_nor_info_init_params(str
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*/
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erase_mask = 0;
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i = 0;
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+#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
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+ if ((info->flags & SECT_4K_PMC) && (mtd->size <=
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+ CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT * 1024)) {
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+ erase_mask |= BIT(i);
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+ spi_nor_set_erase_type(&map->erase_type[i], 4096u,
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+ SPINOR_OP_BE_4K_PMC);
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+ i++;
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+ } else if ((info->flags & SECT_4K) && (mtd->size <=
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+ CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT * 1024)) {
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+ erase_mask |= BIT(i);
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+ spi_nor_set_erase_type(&map->erase_type[i], 4096u,
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+ SPINOR_OP_BE_4K);
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+ i++;
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+ }
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+#else
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if (info->flags & SECT_4K_PMC) {
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erase_mask |= BIT(i);
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spi_nor_set_erase_type(&map->erase_type[i], 4096u,
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@@ -4538,6 +4554,7 @@ static void spi_nor_info_init_params(str
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SPINOR_OP_BE_4K);
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i++;
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}
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+#endif
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erase_mask |= BIT(i);
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spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
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SPINOR_OP_SE);
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