395 lines
12 KiB
Diff
395 lines
12 KiB
Diff
From 4cc24d8a9ac15aceadf2449473494f947c1ead72 Mon Sep 17 00:00:00 2001
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From: Thomas Langer <thomas.langer@lantiq.com>
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Date: Thu, 8 Aug 2013 16:19:15 +0200
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Subject: [PATCH 24/34] GPIO: MIPS: lantiq: add gpio driver for falcon SoC
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Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of
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up to 32 pads. The GPIO blocks have a per pin IRQs.
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Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
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Acked-by: John Crispin <blogic@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Cc: linux-gpio@vger.kernel.org
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---
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drivers/gpio/Kconfig | 5 +
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drivers/gpio/Makefile | 1 +
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drivers/gpio/gpio-falcon.c | 348 ++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 354 insertions(+)
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create mode 100644 drivers/gpio/gpio-falcon.c
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--- a/drivers/gpio/Kconfig
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+++ b/drivers/gpio/Kconfig
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@@ -135,6 +135,11 @@ config GPIO_EP93XX
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depends on ARCH_EP93XX
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select GPIO_GENERIC
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+config GPIO_FALCON
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+ def_bool y
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+ depends on MIPS && SOC_FALCON
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+ select GPIO_GENERIC
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+
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config GPIO_MM_LANTIQ
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bool "Lantiq Memory mapped GPIOs"
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depends on LANTIQ && SOC_XWAY
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--- a/drivers/gpio/Makefile
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+++ b/drivers/gpio/Makefile
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@@ -24,6 +24,7 @@ obj-$(CONFIG_GPIO_DA9055) += gpio-da9055
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obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o
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obj-$(CONFIG_GPIO_EM) += gpio-em.o
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obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
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+obj-$(CONFIG_GPIO_FALCON) += gpio-falcon.o
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obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o
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obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o
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obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
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--- /dev/null
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+++ b/drivers/gpio/gpio-falcon.c
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@@ -0,0 +1,348 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
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+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/gpio.h>
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+#include <linux/interrupt.h>
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+#include <linux/slab.h>
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+#include <linux/export.h>
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+#include <linux/err.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/of_irq.h>
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+#include <linux/pinctrl/pinctrl.h>
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+#include <linux/pinctrl/consumer.h>
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+#include <linux/platform_device.h>
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+
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+#include <lantiq_soc.h>
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+
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+/* Data Output Register */
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+#define GPIO_OUT 0x00000000
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+/* Data Input Register */
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+#define GPIO_IN 0x00000004
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+/* Direction Register */
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+#define GPIO_DIR 0x00000008
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+/* External Interrupt Control Register 0 */
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+#define GPIO_EXINTCR0 0x00000018
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+/* External Interrupt Control Register 1 */
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+#define GPIO_EXINTCR1 0x0000001C
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+/* IRN Capture Register */
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+#define GPIO_IRNCR 0x00000020
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+/* IRN Interrupt Configuration Register */
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+#define GPIO_IRNCFG 0x0000002C
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+/* IRN Interrupt Enable Set Register */
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+#define GPIO_IRNRNSET 0x00000030
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+/* IRN Interrupt Enable Clear Register */
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+#define GPIO_IRNENCLR 0x00000034
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+/* Output Set Register */
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+#define GPIO_OUTSET 0x00000040
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+/* Output Cler Register */
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+#define GPIO_OUTCLR 0x00000044
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+/* Direction Clear Register */
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+#define GPIO_DIRSET 0x00000048
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+/* Direction Set Register */
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+#define GPIO_DIRCLR 0x0000004C
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+
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+/* turn a gpio_chip into a falcon_gpio_port */
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+#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip)
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+/* turn a irq_data into a falcon_gpio_port */
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+#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
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+
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+#define port_r32(p, reg) ltq_r32(p->port + reg)
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+#define port_w32(p, val, reg) ltq_w32(val, p->port + reg)
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+#define port_w32_mask(p, clear, set, reg) \
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+ port_w32(p, (port_r32(p, reg) & ~(clear)) | (set), reg)
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+
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+#define MAX_BANKS 5
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+#define PINS_PER_PORT 32
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+
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+struct falcon_gpio_port {
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+ struct gpio_chip gpio_chip;
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+ void __iomem *port;
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+ unsigned int irq_base;
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+ unsigned int chained_irq;
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+ struct clk *clk;
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+ char name[6];
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+};
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+
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+static struct irq_chip falcon_gpio_irq_chip;
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+
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+static int falcon_gpio_direction_input(struct gpio_chip *chip,
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+ unsigned int offset)
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+{
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+ port_w32(ctop(chip), 1 << offset, GPIO_DIRCLR);
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+
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+ return 0;
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+}
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+
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+static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset,
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+ int value)
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+{
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+ if (value)
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+ port_w32(ctop(chip), 1 << offset, GPIO_OUTSET);
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+ else
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+ port_w32(ctop(chip), 1 << offset, GPIO_OUTCLR);
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+}
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+
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+static int falcon_gpio_direction_output(struct gpio_chip *chip,
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+ unsigned int offset, int value)
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+{
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+ falcon_gpio_set(chip, offset, value);
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+ port_w32(ctop(chip), 1 << offset, GPIO_DIRSET);
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+
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+ return 0;
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+}
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+
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+static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
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+{
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+ if ((port_r32(ctop(chip), GPIO_DIR) >> offset) & 1)
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+ return (port_r32(ctop(chip), GPIO_OUT) >> offset) & 1;
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+ else
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+ return (port_r32(ctop(chip), GPIO_IN) >> offset) & 1;
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+}
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+
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+static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
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+{
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+ int gpio = chip->base + offset;
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+
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+ return pinctrl_request_gpio(gpio);
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+}
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+
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+static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
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+{
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+ int gpio = chip->base + offset;
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+
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+ pinctrl_free_gpio(gpio);
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+}
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+
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+static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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+{
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+ return ctop(chip)->irq_base + offset;
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+}
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+
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+static void falcon_gpio_disable_irq(struct irq_data *d)
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+{
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+ unsigned int offset = d->irq - itop(d)->irq_base;
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+
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+ port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
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+}
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+
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+static void falcon_gpio_enable_irq(struct irq_data *d)
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+{
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+ unsigned int offset = d->irq - itop(d)->irq_base;
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+
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+ port_w32(itop(d), 1 << offset, GPIO_IRNRNSET);
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+}
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+
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+static void falcon_gpio_ack_irq(struct irq_data *d)
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+{
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+ unsigned int offset = d->irq - itop(d)->irq_base;
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+
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+ port_w32(itop(d), 1 << offset, GPIO_IRNCR);
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+}
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+
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+static void falcon_gpio_mask_and_ack_irq(struct irq_data *d)
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+{
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+ unsigned int offset = d->irq - itop(d)->irq_base;
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+
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+ port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
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+ port_w32(itop(d), 1 << offset, GPIO_IRNCR);
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+}
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+
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+static int falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
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+{
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+ unsigned int offset = d->irq - itop(d)->irq_base;
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+ unsigned int mask = 1 << offset;
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+
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+ if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
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+ return 0;
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+
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+ if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
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+ /* level triggered */
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+ port_w32_mask(itop(d), 0, mask, GPIO_IRNCFG);
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+ irq_set_chip_and_handler_name(d->irq,
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+ &falcon_gpio_irq_chip, handle_level_irq, "mux");
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+ } else {
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+ /* edge triggered */
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+ port_w32_mask(itop(d), mask, 0, GPIO_IRNCFG);
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+ irq_set_chip_and_handler_name(d->irq,
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+ &falcon_gpio_irq_chip, handle_simple_irq, "mux");
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+ }
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+
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+ if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
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+ port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
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+ port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR1);
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+ } else {
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+ if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
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+ /* positive logic: rising edge, high level */
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+ port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
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+ else
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+ /* negative logic: falling edge, low level */
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+ port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR0);
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+ port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR1);
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+ }
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+
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+ return gpio_direction_input(itop(d)->gpio_chip.base + offset);
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+}
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+
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+static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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+{
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+ struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
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+ unsigned long irncr;
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+ int offset;
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+
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+ /* acknowledge interrupt */
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+ irncr = port_r32(gpio_port, GPIO_IRNCR);
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+ port_w32(gpio_port, irncr, GPIO_IRNCR);
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+
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+ desc->irq_data.chip->irq_ack(&desc->irq_data);
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+
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+ for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
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+ generic_handle_irq(gpio_port->irq_base + offset);
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+}
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+
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+static int falcon_gpio_irq_map(struct irq_domain *d, unsigned int irq,
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+ irq_hw_number_t hw)
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+{
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+ struct falcon_gpio_port *port = d->host_data;
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+
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+ irq_set_chip_and_handler_name(irq, &falcon_gpio_irq_chip,
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+ handle_simple_irq, "mux");
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+ irq_set_chip_data(irq, port);
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+
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+ /* set to negative logic (falling edge, low level) */
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+ port_w32_mask(port, 0, 1 << hw, GPIO_EXINTCR0);
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+ return 0;
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+}
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+
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+static struct irq_chip falcon_gpio_irq_chip = {
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+ .name = "gpio_irq_mux",
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+ .irq_mask = falcon_gpio_disable_irq,
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+ .irq_unmask = falcon_gpio_enable_irq,
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+ .irq_ack = falcon_gpio_ack_irq,
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+ .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
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+ .irq_set_type = falcon_gpio_irq_type,
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+};
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+
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+static const struct irq_domain_ops irq_domain_ops = {
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+ .xlate = irq_domain_xlate_onetwocell,
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+ .map = falcon_gpio_irq_map,
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+};
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+
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+static struct irqaction gpio_cascade = {
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+ .handler = no_action,
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+ .flags = IRQF_DISABLED,
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+ .name = "gpio_cascade",
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+};
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+
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+static int falcon_gpio_probe(struct platform_device *pdev)
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+{
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+ struct pinctrl_gpio_range *gpio_range;
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+ struct device_node *node = pdev->dev.of_node;
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+ const __be32 *bank = of_get_property(node, "lantiq,bank", NULL);
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+ struct falcon_gpio_port *gpio_port;
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+ struct resource *gpiores, irqres;
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+ int ret, size;
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+
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+ if (!bank || *bank >= MAX_BANKS)
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+ return -ENODEV;
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+
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+ size = pinctrl_falcon_get_range_size(*bank);
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+ if (size < 1) {
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+ dev_err(&pdev->dev, "pad not loaded for bank %d\n", *bank);
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+ return size;
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+ }
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+
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+ gpio_range = devm_kzalloc(&pdev->dev, sizeof(struct pinctrl_gpio_range),
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+ GFP_KERNEL);
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+ if (!gpio_range)
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+ return -ENOMEM;
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+
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+ gpio_port = devm_kzalloc(&pdev->dev, sizeof(struct falcon_gpio_port),
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+ GFP_KERNEL);
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+ if (!gpio_port)
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+ return -ENOMEM;
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+
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+ snprintf(gpio_port->name, 6, "gpio%d", *bank);
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+ gpio_port->gpio_chip.label = gpio_port->name;
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+ gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
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+ gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
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+ gpio_port->gpio_chip.get = falcon_gpio_get;
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+ gpio_port->gpio_chip.set = falcon_gpio_set;
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+ gpio_port->gpio_chip.request = falcon_gpio_request;
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+ gpio_port->gpio_chip.free = falcon_gpio_free;
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+ gpio_port->gpio_chip.base = *bank * PINS_PER_PORT;
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+ gpio_port->gpio_chip.ngpio = size;
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+ gpio_port->gpio_chip.dev = &pdev->dev;
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+
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+ gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ gpio_port->port = devm_request_and_ioremap(&pdev->dev, gpiores);
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+ if (IS_ERR(gpio_port->port))
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+ return PTR_ERR(gpio_port->port);
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+
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+ gpio_port->clk = devm_clk_get(&pdev->dev, NULL);
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+ if (IS_ERR(gpio_port->clk))
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+ return PTR_ERR(gpio_port->clk);
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+ clk_activate(gpio_port->clk);
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+
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+ if (of_irq_to_resource_table(node, &irqres, 1) == 1) {
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+ gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * *bank);
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+ gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
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+ gpio_port->chained_irq = irqres.start;
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+ irq_domain_add_legacy(node, size, gpio_port->irq_base, 0,
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+ &irq_domain_ops, gpio_port);
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+ setup_irq(irqres.start, &gpio_cascade);
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+ irq_set_handler_data(irqres.start, gpio_port);
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+ irq_set_chained_handler(irqres.start, falcon_gpio_irq_handler);
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+ }
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+
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+ ret = gpiochip_add(&gpio_port->gpio_chip);
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+ if (ret)
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+ return ret;
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+
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+ platform_set_drvdata(pdev, gpio_port);
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+
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+ gpio_range->name = "FALCON GPIO";
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+ gpio_range->id = *bank;
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+ gpio_range->base = gpio_port->gpio_chip.base;
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+ gpio_range->pin_base = gpio_port->gpio_chip.base;
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+ gpio_range->npins = gpio_port->gpio_chip.ngpio;
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+ gpio_range->gc = &gpio_port->gpio_chip;
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+
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+ pinctrl_falcon_add_gpio_range(gpio_range);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id falcon_gpio_match[] = {
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+ { .compatible = "lantiq,falcon-gpio" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, falcon_gpio_match);
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+
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+static struct platform_driver falcon_gpio_driver = {
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+ .probe = falcon_gpio_probe,
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+ .driver = {
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+ .name = "gpio-falcon",
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+ .owner = THIS_MODULE,
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+ .of_match_table = falcon_gpio_match,
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+ },
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+};
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+
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+int __init falcon_gpio_init(void)
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+{
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+ int ret;
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+
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+ pr_info("FALC(tm) ON GPIO Driver, (C) 2012 Lantiq Deutschland Gmbh\n");
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+ ret = platform_driver_register(&falcon_gpio_driver);
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+ if (ret)
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+ pr_err("falcon_gpio: Error registering platform driver!");
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+ return ret;
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+}
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+
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+subsys_initcall(falcon_gpio_init);
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