d62825dd77
fa731838c5cleared the forced speed in the QSGMII PCS_ALL_CH_CTL register during probe, but this is only correct for GMACs that are not configured with fixed-link. This prevented GMACs configured with both phy-mode = "sgmii" and fixed-link from working properly, as discussed at https://github.com/openwrt/openwrt/pull/3954#issuecomment-834625090 and the comments that follow. Notably, this prevented all communication between gmac2 and the switch on the Netgear R7800. The correct behavior is to set the QSGMII PCS_ALL_CH_CTL register by considering the gmac's fixed-link child, setting the speed as directed by fixed-link if present, and otherwise clearing it as was done previously. Fixes:fa731838c5("ipq806x: dwmac: clear forced speed during probe") Signed-off-by: Mark Mentovai <mark@moxienet.com> Tested-by: Hannu Nyman <hannu.nyman@iki.fi> Run-tested: ipq806x/ubnt,unifi-ac-hd, ipq806x/netgear,r7800 Cc: Petr Štetiar <ynezz@true.cz> Cc: Ansuel Smith <ansuelsmth@gmail.com> Tested-by: Ansuel Smith <ansuelsmth@gmail.com>
84 lines
2.4 KiB
Diff
84 lines
2.4 KiB
Diff
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
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@@ -64,6 +64,17 @@
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#define NSS_COMMON_CLK_DIV_SGMII_100 4
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#define NSS_COMMON_CLK_DIV_SGMII_10 49
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+#define QSGMII_PCS_ALL_CH_CTL 0x80
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+#define QSGMII_PCS_CH_SPEED_FORCE 0x2
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+#define QSGMII_PCS_CH_SPEED_10 0x0
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+#define QSGMII_PCS_CH_SPEED_100 0x4
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+#define QSGMII_PCS_CH_SPEED_1000 0x8
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+#define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \
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+ QSGMII_PCS_CH_SPEED_10 | \
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+ QSGMII_PCS_CH_SPEED_100 | \
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+ QSGMII_PCS_CH_SPEED_1000)
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+#define QSGMII_PCS_CH_SPEED_SHIFT(x) (x * 4)
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+
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#define QSGMII_PCS_CAL_LCKDT_CTL 0x120
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#define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19)
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@@ -241,6 +252,36 @@ static void ipq806x_gmac_fix_mac_speed(v
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ipq806x_gmac_set_speed(gmac, speed);
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}
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+static int
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+ipq806x_gmac_get_qsgmii_pcs_speed_val(struct platform_device *pdev) {
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+ struct device_node *fixed_link_node;
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+ int rv;
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+ int fixed_link_speed;
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+
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+ if (!of_phy_is_fixed_link(pdev->dev.of_node))
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+ return 0;
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+
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+ fixed_link_node = of_get_child_by_name(pdev->dev.of_node, "fixed-link");
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+ if (!fixed_link_node)
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+ return -1;
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+
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+ rv = of_property_read_u32(fixed_link_node, "speed", &fixed_link_speed);
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+ of_node_put(fixed_link_node);
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+ if (rv)
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+ return -1;
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+
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+ switch (fixed_link_speed) {
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+ case SPEED_1000:
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+ return QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_1000;
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+ case SPEED_100:
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+ return QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_100;
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+ case SPEED_10:
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+ return QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_10;
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+ }
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+
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+ return -1;
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+}
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+
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static int ipq806x_gmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat_dat;
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@@ -249,6 +290,7 @@ static int ipq806x_gmac_probe(struct pla
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struct ipq806x_gmac *gmac;
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int val;
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int err;
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+ int qsgmii_pcs_speed;
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val = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (val)
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@@ -345,6 +387,17 @@ static int ipq806x_gmac_probe(struct pla
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0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |
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0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |
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0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);
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+
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+ qsgmii_pcs_speed = ipq806x_gmac_get_qsgmii_pcs_speed_val(pdev);
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+ if (qsgmii_pcs_speed != -1) {
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+ regmap_update_bits(
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+ gmac->qsgmii_csr,
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+ QSGMII_PCS_ALL_CH_CTL,
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+ QSGMII_PCS_CH_SPEED_MASK <<
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+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id),
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+ qsgmii_pcs_speed <<
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+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id));
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+ }
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}
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plat_dat->has_gmac = true;
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