667f6c7f49
Manually rebased patches:
bcm27xx/patches-5.4/950-0135-spi-spi-bcm2835-Disable-forced-software-CS.patch
generic-backport/744-v5.5-net-sfp-soft-status-and-control-support.patch
layerscape/patches-5.4/819-uart-0005-tty-serial-fsl_lpuart-enable-dma-mode-for-imx8qxp.patch
mvebu/patches-5.4/521-arm64-dts-marvell-espressobin-Add-ethernet-switch-al.patch
Removed:
layerscape/patches-5.4/819-uart-0012-tty-serial-lpuart-add-LS1028A-support.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
lantiq/Easybox 904 xDSL, x86_64
Run-tested: ipq806x/R7800, lantiq/Easybox 904 xDSL, x86_64
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
Co-developed-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
418 lines
15 KiB
Diff
418 lines
15 KiB
Diff
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To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
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Subject: [PATCH v2 3/4] arm64: dts: mediatek: Split PCIe node for
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MT2712/MT7622
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Date: Thu, 28 May 2020 14:16:47 +0800
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srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
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From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
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There are two independent PCIe controllers in MT2712/MT7622 platform,
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and each of them should contain an independent MSI domain.
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In current architecture, MSI domain will be inherited from the root
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bridge, and all of the devices will share the same MSI domain.
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Hence that, the PCIe devices will not work properly if the irq number
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which required is more than 32.
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Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
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comply with the hardware design.
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Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
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---
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arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 75 +++++++++++--------
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.../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 ++--
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arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +-
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 68 +++++++++++------
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4 files changed, 96 insertions(+), 69 deletions(-)
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--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
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@@ -791,60 +791,73 @@
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};
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};
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- pcie: pcie@11700000 {
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+ pcie1: pcie@112ff000 {
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compatible = "mediatek,mt2712-pcie";
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device_type = "pci";
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- reg = <0 0x11700000 0 0x1000>,
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- <0 0x112ff000 0 0x1000>;
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- reg-names = "port0", "port1";
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+ reg = <0 0x112ff000 0 0x1000>;
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+ reg-names = "port1";
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#address-cells = <3>;
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#size-cells = <2>;
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- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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- <&pericfg CLK_PERI_PCIE0>,
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+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie_irq";
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+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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<&pericfg CLK_PERI_PCIE1>;
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- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
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- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
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- phy-names = "pcie-phy0", "pcie-phy1";
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+ clock-names = "sys_ck1", "ahb_ck1";
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+ phys = <&u3port1 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy1";
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bus-range = <0x00 0xff>;
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- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
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+ status = "disabled";
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- pcie0: pcie@0,0 {
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- device_type = "pci";
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- status = "disabled";
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- reg = <0x0000 0 0 0 0>;
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+ slot1: pcie@1,0 {
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+ reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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- <0 0 0 2 &pcie_intc0 1>,
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- <0 0 0 3 &pcie_intc0 2>,
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- <0 0 0 4 &pcie_intc0 3>;
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- pcie_intc0: interrupt-controller {
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+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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+ <0 0 0 2 &pcie_intc1 1>,
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+ <0 0 0 3 &pcie_intc1 2>,
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+ <0 0 0 4 &pcie_intc1 3>;
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+ pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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+ };
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- pcie1: pcie@1,0 {
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- device_type = "pci";
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- status = "disabled";
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- reg = <0x0800 0 0 0 0>;
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+ pcie0: pcie@11700000 {
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+ compatible = "mediatek,mt2712-pcie";
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+ device_type = "pci";
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+ reg = <0 0x11700000 0 0x1000>;
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+ reg-names = "port0";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie_irq";
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+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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+ <&pericfg CLK_PERI_PCIE0>;
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+ clock-names = "sys_ck0", "ahb_ck0";
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+ phys = <&u3port0 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy0";
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ status = "disabled";
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+
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+ slot0: pcie@0,0 {
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+ reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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- <0 0 0 2 &pcie_intc1 1>,
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- <0 0 0 3 &pcie_intc1 2>,
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- <0 0 0 4 &pcie_intc1 3>;
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- pcie_intc1: interrupt-controller {
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+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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+ <0 0 0 2 &pcie_intc0 1>,
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+ <0 0 0 3 &pcie_intc0 2>,
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+ <0 0 0 4 &pcie_intc0 3>;
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+ pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
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@@ -294,18 +294,16 @@
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};
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};
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-&pcie {
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+&pcie0 {
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pinctrl-names = "default";
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- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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+ pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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+};
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- pcie@0,0 {
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- status = "okay";
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- };
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-
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- pcie@1,0 {
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- status = "okay";
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- };
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+&pcie1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie1_pins>;
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+ status = "okay";
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};
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|
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&pio {
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -792,45 +792,41 @@
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#reset-cells = <1>;
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};
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- pcie: pcie@1a140000 {
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+ pciecfg: pciecfg@1a140000 {
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+ compatible = "mediatek,mt7622-pciecfg", "syscon";
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+ reg = <0 0x1a140000 0 0x1000>;
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+ };
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+
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+ pcie0: pcie@1a143000 {
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compatible = "mediatek,mt7622-pcie";
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device_type = "pci";
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- reg = <0 0x1a140000 0 0x1000>,
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- <0 0x1a143000 0 0x1000>,
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- <0 0x1a145000 0 0x1000>;
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- reg-names = "subsys", "port0", "port1";
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+ reg = <0 0x1a143000 0 0x1000>;
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+ reg-names = "port0";
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+ mediatek,pcie-cfg = <&pciecfg>;
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#address-cells = <3>;
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#size-cells = <2>;
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- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
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- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "pcie_irq";
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clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
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- <&pciesys CLK_PCIE_P1_MAC_EN>,
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- <&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P0_AUX_EN>,
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- <&pciesys CLK_PCIE_P1_AUX_EN>,
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<&pciesys CLK_PCIE_P0_AXI_EN>,
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- <&pciesys CLK_PCIE_P1_AXI_EN>,
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<&pciesys CLK_PCIE_P0_OBFF_EN>,
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- <&pciesys CLK_PCIE_P1_OBFF_EN>,
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- <&pciesys CLK_PCIE_P0_PIPE_EN>,
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- <&pciesys CLK_PCIE_P1_PIPE_EN>;
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- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
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|
- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
|
|
- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
|
|
+ <&pciesys CLK_PCIE_P0_PIPE_EN>;
|
|
+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
|
|
+ "axi_ck0", "obff_ck0", "pipe_ck0";
|
|
+
|
|
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
|
bus-range = <0x00 0xff>;
|
|
- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
|
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
|
|
status = "disabled";
|
|
|
|
- pcie0: pcie@0,0 {
|
|
+ slot0: pcie@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges;
|
|
- status = "disabled";
|
|
-
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
|
<0 0 0 2 &pcie_intc0 1>,
|
|
@@ -842,15 +838,39 @@
|
|
#interrupt-cells = <1>;
|
|
};
|
|
};
|
|
+ };
|
|
|
|
- pcie1: pcie@1,0 {
|
|
+ pcie1: pcie@1a145000 {
|
|
+ compatible = "mediatek,mt7622-pcie";
|
|
+ device_type = "pci";
|
|
+ reg = <0 0x1a145000 0 0x1000>;
|
|
+ reg-names = "port1";
|
|
+ mediatek,pcie-cfg = <&pciecfg>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
|
+ interrupt-names = "pcie_irq";
|
|
+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
|
|
+ /* designer has connect RC1 with p0_ahb clock */
|
|
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
|
|
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
|
|
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
|
|
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
|
|
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
|
|
+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
|
|
+ "axi_ck1", "obff_ck1", "pipe_ck1";
|
|
+
|
|
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
|
+ bus-range = <0x00 0xff>;
|
|
+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
|
|
+ status = "disabled";
|
|
+
|
|
+ slot1: pcie@1,0 {
|
|
reg = <0x0800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges;
|
|
- status = "disabled";
|
|
-
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
|
<0 0 0 2 &pcie_intc1 1>,
|
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
|
@@ -254,18 +254,16 @@
|
|
};
|
|
};
|
|
|
|
-&pcie {
|
|
+&pcie0 {
|
|
pinctrl-names = "default";
|
|
- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
|
|
+ pinctrl-0 = <&pcie0_pins>;
|
|
status = "okay";
|
|
+};
|
|
|
|
- pcie@0,0 {
|
|
- status = "okay";
|
|
- };
|
|
-
|
|
- pcie@1,0 {
|
|
- status = "okay";
|
|
- };
|
|
+&pcie1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie1_pins>;
|
|
+ status = "okay";
|
|
};
|
|
|
|
&pio {
|