770a9c6787
All modifications made by update_kernel.sh/no manual intervention needed Run-tested: ipq806x (R7800), ath79 (Archer C7v5), x86/64 No dmesg regressions, everything appears functional Signed-off-by: John Audia <graysky@archlinux.us> [add run test from PR] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
45 lines
1.2 KiB
Diff
45 lines
1.2 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
|
@@ -865,6 +865,41 @@
|
|
reg = <0x12100000 0x10000>;
|
|
};
|
|
|
|
+ gsbi1: gsbi@12440000 {
|
|
+ compatible = "qcom,gsbi-v1.0.0";
|
|
+ cell-index = <1>;
|
|
+ reg = <0x12440000 0x100>;
|
|
+ clocks = <&gcc GSBI1_H_CLK>;
|
|
+ clock-names = "iface";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ syscon-tcsr = <&tcsr>;
|
|
+
|
|
+ gsbi1_serial: serial@12450000 {
|
|
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
+ reg = <0x12450000 0x100>,
|
|
+ <0x12400000 0x03>;
|
|
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gsbi1_i2c: i2c@12460000 {
|
|
+ compatible = "qcom,i2c-qup-v1.1.1";
|
|
+ reg = <0x12460000 0x1000>;
|
|
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
gsbi2: gsbi@12480000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <2>;
|