77e97abf12
Also removes random module and switches to new bcm2711 thermal driver. Boot tested on RPi 4B v1.1 4G. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
72 lines
2.3 KiB
Diff
72 lines
2.3 KiB
Diff
From 1ee90bb75979c183e241c14f7c31d72cdb4bcc9b Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 2 May 2019 15:24:04 -0700
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Subject: [PATCH] clk: bcm2835: Allow reparenting leaf clocks while
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they're running.
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This falls under the same "we can reprogram glitch-free as long as we
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pause generation" rule as updating the div/frac fields. This can be
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used for runtime reclocking of V3D to manage power leakage.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/clk/bcm/clk-bcm2835.c | 19 ++++++++++++++++---
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1 file changed, 16 insertions(+), 3 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1087,8 +1087,10 @@ static int bcm2835_clock_on(struct clk_h
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return 0;
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}
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-static int bcm2835_clock_set_rate(struct clk_hw *hw,
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- unsigned long rate, unsigned long parent_rate)
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+static int bcm2835_clock_set_rate_and_parent(struct clk_hw *hw,
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+ unsigned long rate,
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+ unsigned long parent_rate,
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+ u8 parent)
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{
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struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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struct bcm2835_cprman *cprman = clock->cprman;
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@@ -1110,6 +1112,11 @@ static int bcm2835_clock_set_rate(struct
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bcm2835_clock_wait_busy(clock);
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}
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+ if (parent != 0xff) {
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+ ctl &= ~(CM_SRC_MASK << CM_SRC_SHIFT);
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+ ctl |= parent << CM_SRC_SHIFT;
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+ }
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+
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ctl &= ~CM_FRAC;
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ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
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cprman_write(cprman, data->ctl_reg, ctl);
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@@ -1121,6 +1128,12 @@ static int bcm2835_clock_set_rate(struct
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return 0;
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}
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+static int bcm2835_clock_set_rate(struct clk_hw *hw,
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+ unsigned long rate, unsigned long parent_rate)
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+{
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+ return bcm2835_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff);
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+}
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+
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static bool
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bcm2835_clk_is_pllc(struct clk_hw *hw)
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{
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@@ -1304,6 +1317,7 @@ static const struct clk_ops bcm2835_cloc
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.unprepare = bcm2835_clock_off,
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.recalc_rate = bcm2835_clock_get_rate,
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.set_rate = bcm2835_clock_set_rate,
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+ .set_rate_and_parent = bcm2835_clock_set_rate_and_parent,
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.determine_rate = bcm2835_clock_determine_rate,
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.set_parent = bcm2835_clock_set_parent,
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.get_parent = bcm2835_clock_get_parent,
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@@ -1480,7 +1494,6 @@ static struct clk_hw *bcm2835_register_c
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init.ops = &bcm2835_vpu_clock_clk_ops;
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} else {
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init.ops = &bcm2835_clock_clk_ops;
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- init.flags |= CLK_SET_PARENT_GATE;
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/* If the clock wasn't actually enabled at boot, it's not
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* critical.
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