c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
104 lines
2.9 KiB
Diff
104 lines
2.9 KiB
Diff
From 5d06e90bd0e3bdd104b7b25173e05617f02dc44d Mon Sep 17 00:00:00 2001
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From: Alison Wang <b18965@freescale.com>
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Date: Fri, 13 May 2016 15:09:47 +0800
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Subject: [PATCH 08/70] armv8: aarch32: Add SMP support for 32-bit Linux
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The patch adds SMP support for running 32-bit Linux kernel. Spin-table
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method is used for SMP support.
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Signed-off-by: Alison Wang <alison.wang@nxp.com>
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Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
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---
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arch/arm/mach-imx/common.h | 1 +
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arch/arm/mach-imx/mach-ls1043a.c | 1 +
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arch/arm/mach-imx/platsmp.c | 49 ++++++++++++++++++++++++++++++++++++++
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3 files changed, 51 insertions(+)
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--- a/arch/arm/mach-imx/common.h
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+++ b/arch/arm/mach-imx/common.h
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@@ -155,5 +155,6 @@ static inline void imx_init_l2cache(void
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extern struct smp_operations imx_smp_ops;
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extern struct smp_operations ls1021a_smp_ops;
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+extern const struct smp_operations layerscape_smp_ops;
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#endif
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--- a/arch/arm/mach-imx/mach-ls1043a.c
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+++ b/arch/arm/mach-imx/mach-ls1043a.c
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@@ -17,5 +17,6 @@ static const char * const ls1043a_dt_com
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};
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DT_MACHINE_START(LS1043A, "Freescale LS1043A")
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+ .smp = smp_ops(layerscape_smp_ops),
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.dt_compat = ls1043a_dt_compat,
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MACHINE_END
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--- a/arch/arm/mach-imx/platsmp.c
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+++ b/arch/arm/mach-imx/platsmp.c
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@@ -14,6 +14,7 @@
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#include <linux/of_address.h>
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#include <linux/of.h>
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#include <linux/smp.h>
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+#include <linux/types.h>
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#include <asm/cacheflush.h>
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#include <asm/page.h>
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@@ -26,6 +27,8 @@
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u32 g_diag_reg;
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static void __iomem *scu_base;
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+static u64 cpu_release_addr[NR_CPUS];
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+
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static struct map_desc scu_io_desc __initdata = {
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/* .virtual and .pfn are run-time assigned */
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.length = SZ_4K,
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@@ -127,3 +130,49 @@ struct smp_operations ls1021a_smp_ops _
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.smp_prepare_cpus = ls1021a_smp_prepare_cpus,
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.smp_boot_secondary = ls1021a_boot_secondary,
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};
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+
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+static int layerscape_smp_boot_secondary(unsigned int cpu,
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+ struct task_struct *idle)
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+{
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+ u32 secondary_startup_phys;
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+ __le32 __iomem *release_addr;
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+
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+ secondary_startup_phys = virt_to_phys(secondary_startup);
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+
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+ release_addr = ioremap_cache((u32)cpu_release_addr[cpu],
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+ sizeof(u64));
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+ if (!release_addr)
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+ return -ENOMEM;
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+
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+ writel_relaxed(secondary_startup_phys, release_addr);
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+ writel_relaxed(0, release_addr + 1);
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+ __cpuc_flush_dcache_area((__force void *)release_addr,
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+ sizeof(u64));
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+
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+ sev();
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+
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+ iounmap(release_addr);
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+
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+ return 0;
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+}
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+
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+static void layerscape_smp_init_cpus(void)
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+{
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+ struct device_node *dnt = NULL;
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+ unsigned int cpu = 0;
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+
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+ while ((dnt = of_find_node_by_type(dnt, "cpu"))) {
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+ if (of_property_read_u64(dnt, "cpu-release-addr",
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+ &cpu_release_addr[cpu])) {
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+ pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
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+ cpu);
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+ }
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+
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+ cpu++;
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+ }
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+}
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+
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+const struct smp_operations layerscape_smp_ops __initconst = {
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+ .smp_init_cpus = layerscape_smp_init_cpus,
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+ .smp_boot_secondary = layerscape_smp_boot_secondary,
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+};
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