Openwrt/target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts
Adrian Schmutzler 3a4b751110 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-02-24 02:53:53 +01:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ar9344.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "compex,wpj344-16m", "qca,ar9344";
model = "Compex WPJ344 (16MB flash)";
aliases {
label-mac-device = &eth0;
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
};
leds {
compatible = "gpio-leds";
led_status: status {
label = "green:status";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
};
sig1 {
label = "red:sig1";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
sig2 {
label = "yellow:sig2";
gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
};
sig3 {
label = "green:sig3";
gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
};
sig4 {
label = "green:sig4";
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
linux,code = <KEY_RESTART>;
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
};
&ref {
clock-frequency = <40000000>;
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
uboot: partition@0 {
label = "u-boot";
reg = <0x000000 0x030000>;
read-only;
};
partition@30000 {
label = "firmware";
reg = <0x030000 0xfc0000>;
compatible = "denx,uimage";
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&usb {
status = "okay";
};
&usb_phy {
status = "okay";
};
&pcie {
status = "okay";
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
};
&mdio0 {
status = "okay";
phy-mask = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "rgmii";
qca,ar8327-initvals = <
0x04 0x07600000 /* PORT0 PAD MODE CTRL */
0x10 0x80000080 /* POWER_ON_STRAP */
0x50 0x00000000 /* LED_CTRL0 */
0x54 0xc737c737 /* LED_CTRL1 */
0x58 0x00000000 /* LED_CTRL2 */
0x5c 0x00c30c00 /* LED_CTRL3 */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
};
&eth0 {
status = "okay";
pll-data = <0x06000000 0x00000101 0x00001616>;
mtd-mac-address = <&uboot 0x2e010>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};