c9ae111a20
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.12, and Linux v3.13. This work mainly covers: * Finishes work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family, and the Armada family. * timer initialization update, and access function for the Armada family. * Generic IRQ handling backporting. * Some bug fixes. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39566
86 lines
3.5 KiB
Diff
86 lines
3.5 KiB
Diff
From b2ea44bd7bca49fe5696857327a1d1514edd1196 Mon Sep 17 00:00:00 2001
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From: Arnaud Ebalard <arno@natisbad.org>
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Date: Tue, 5 Nov 2013 21:45:48 +0100
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Subject: [PATCH 202/203] ARM: mvebu: second PCIe unit of Armada XP mv78230 is
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only x1 capable
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Various Marvell datasheets advertise second PCIe unit of mv78230
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flavour of Armada XP as x4/quad x1 capable. This second unit is in
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fact only x1 capable. This patch fixes current mv78230 .dtsi to
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reflect that, i.e. makes 1.0 the second interface (instead of 2.0
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at the moment). This was successfully tested on a mv78230-based
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ReadyNAS 2120 platform with a x1 device (FL1009 XHCI controller)
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connected to this second interface.
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Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
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Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Cc: <stable@vger.kernel.org> # v3.10.x
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Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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---
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arch/arm/boot/dts/armada-xp-mv78230.dtsi | 24 ++++++++++++------------
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1 file changed, 12 insertions(+), 12 deletions(-)
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--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
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+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
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@@ -47,7 +47,7 @@
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/*
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* MV78230 has 2 PCIe units Gen2.0: One unit can be
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* configured as x4 or quad x1 lanes. One unit is
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- * x4/x1.
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+ * x1 only.
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*/
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pcie-controller {
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compatible = "marvell,armada-xp-pcie";
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@@ -62,10 +62,10 @@
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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- 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
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+ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
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@@ -74,8 +74,8 @@
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0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
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0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
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0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
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- 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
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- 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
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+ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
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+ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
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pcie@1,0 {
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device_type = "pci";
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@@ -145,20 +145,20 @@
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status = "disabled";
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};
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- pcie@9,0 {
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+ pcie@5,0 {
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device_type = "pci";
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- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
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- reg = <0x4800 0 0 0 0>;
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+ assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
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+ reg = <0x2800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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- ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
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- 0x81000000 0 0 0x81000000 0x9 0 1 0>;
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+ ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
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+ 0x81000000 0 0 0x81000000 0x5 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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- interrupt-map = <0 0 0 0 &mpic 99>;
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- marvell,pcie-port = <2>;
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+ interrupt-map = <0 0 0 0 &mpic 62>;
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+ marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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- clocks = <&gateclk 26>;
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+ clocks = <&gateclk 9>;
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status = "disabled";
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};
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};
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