b4c02c9998
Removed upstreamed patches:
generic/pending-5.4
445-mtd-spinand-gigadevice-Only-one-dummy-byte-in-QUA.patch
446-mtd-spinand-gigadevice-Add-QE-Bit.patch
pistachio/patches-5.4
150-pwm-img-Fix-null-pointer-access-in-probe.patch
Manually rebased:
layerscape/patches-5.4
801-audio-0011-Revert-ASoC-fsl_sai-add-of_match-data.patch
801-audio-0039-MLK-16224-6-ASoC-fsl_sai-fix-DSD-suspend-resume.patch
801-audio-0073-MLK-21957-3-ASoC-fsl_sai-add-bitcount-and-timestamp-.patch
820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh.patch
All modifications made by update_kernel.sh
Build system: x86_64
Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711,
mvebu (mamba, rango), x86_64, ramips/mt7621
Run-tested: ipq806x/R7800, mvebu (mamba, rango), x86_64, ramips (RT-AC57U)
No dmesg regressions, everything functional
Signed-off-by: John Audia <graysky@archlinux.us>
[alter 820-usb-0009-usb-dwc3-Add-workaround-for-host-mode-VBUS-glitch-wh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
32 lines
1.2 KiB
Diff
32 lines
1.2 KiB
Diff
From e9d49d1b54bb1f202ac8d4a42c5ebb9a9237da17 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.org>
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Date: Wed, 31 Oct 2018 14:56:59 +0000
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Subject: [PATCH] media: tc358743: Increase FIFO level to 374.
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The existing fixed value of 16 worked for UYVY 720P60 over
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2 lanes at 594MHz, or UYVY 1080P60 over 4 lanes. (RGB888
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1080P60 needs 6 lanes at 594MHz).
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It doesn't allow for lower resolutions to work as the FIFO
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underflows.
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374 is required for 1080P24-30 UYVY over 2 lanes @ 972Mbit/s, but
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>374 means that the FIFO underflows on 1080P50 UYVY over 2 lanes
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@ 972Mbit/s.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
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---
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drivers/media/i2c/tc358743.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/media/i2c/tc358743.c
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+++ b/drivers/media/i2c/tc358743.c
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@@ -1949,7 +1949,7 @@ static int tc358743_probe_of(struct tc35
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state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
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state->pdata.enable_hdcp = false;
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/* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
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- state->pdata.fifo_level = 16;
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+ state->pdata.fifo_level = 374;
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/*
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* The PLL input clock is obtained by dividing refclk by pll_prd.
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* It must be between 6 MHz and 40 MHz, lower frequency is better.
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