ad907e1c03
Add support for NXP layerscape ls1046ardb 64b/32b Dev board. LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot * USB 3.0: one super speed USB 3.0 type A port, one Micro-AB port * UART: supports two UARTs up to 115200 bps for console Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
54 lines
1.7 KiB
Diff
54 lines
1.7 KiB
Diff
From 5cd461cd17c3e27e5501e499d5d865b60ee58257 Mon Sep 17 00:00:00 2001
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From: Gong Qianyu <Qianyu.Gong@nxp.com>
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Date: Mon, 26 Sep 2016 12:29:24 +0800
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Subject: [PATCH 130/141] ls1046a/sata: Add LS1046A sata support
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Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
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Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
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Integated-by: Yutang Jiang <yutang.jiang@nxp.com>
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---
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drivers/ata/ahci_qoriq.c | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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--- a/drivers/ata/ahci_qoriq.c
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+++ b/drivers/ata/ahci_qoriq.c
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@@ -40,11 +40,16 @@
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#define AHCI_PORT_PHY_5_CFG 0x192c96a4
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#define AHCI_PORT_TRANS_CFG 0x08000025
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+/* for ls1046a */
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+#define LS1046A_PORT_PHY2 0x28184d1f
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+#define LS1046A_PORT_PHY3 0x0e081509
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+
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#define SATA_ECC_DISABLE 0x00020000
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enum ahci_qoriq_type {
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AHCI_LS1021A,
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AHCI_LS1043A,
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+ AHCI_LS1046A,
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AHCI_LS2080A,
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};
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@@ -57,6 +62,7 @@ struct ahci_qoriq_priv {
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static const struct of_device_id ahci_qoriq_of_match[] = {
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{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
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{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
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+ { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
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{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
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{},
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};
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@@ -158,6 +164,13 @@ static int ahci_qoriq_phy_init(struct ah
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writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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break;
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+ case AHCI_LS1046A:
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+ writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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+ writel(LS1046A_PORT_PHY2, reg_base + PORT_PHY2);
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+ writel(LS1046A_PORT_PHY3, reg_base + PORT_PHY3);
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+ writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
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+ break;
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+
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case AHCI_LS1043A:
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case AHCI_LS2080A:
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writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
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