c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
27 lines
902 B
Diff
27 lines
902 B
Diff
From 31a5b5189bdd33bb87f88320964a47c0da983af2 Mon Sep 17 00:00:00 2001
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From: Jianhua Xie <jianhua.xie@nxp.com>
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Date: Fri, 29 Jan 2016 16:40:46 +0800
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Subject: [PATCH 10/70] arm: add pgprot_cached and pgprot_cached_ns support
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Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
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---
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arch/arm/include/asm/pgtable.h | 7 +++++++
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1 file changed, 7 insertions(+)
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--- a/arch/arm/include/asm/pgtable.h
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+++ b/arch/arm/include/asm/pgtable.h
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@@ -116,6 +116,13 @@ extern pgprot_t pgprot_s2_device;
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#define pgprot_noncached(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
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+#define pgprot_cached(prot) \
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+ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED)
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+
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+#define pgprot_cached_ns(prot) \
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+ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \
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+ L_PTE_MT_DEV_NONSHARED)
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+
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#define pgprot_writecombine(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
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