c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
72 lines
2.5 KiB
Diff
72 lines
2.5 KiB
Diff
From 6882f9eef932e6f5cc3c57115e3d7d4b5bc19662 Mon Sep 17 00:00:00 2001
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From: Bjorn Helgaas <bhelgaas@google.com>
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Date: Tue, 5 Jan 2016 15:56:30 -0600
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Subject: [PATCH 53/70] PCI: designware: Make config accessor override
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checking symmetric
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Drivers based on the DesignWare core can override the config read accessors
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by supplying rd_own_conf() and rd_other_conf() function pointers.
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dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root
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bus) or dw_pcie_rd_other_conf():
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dw_pcie_rd_conf
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dw_pcie_rd_own_conf # if on root bus
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dw_pcie_rd_other_conf # if not on root bus
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Previously we checked for rd_other_conf() directly in dw_pcie_rd_conf(),
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but we checked for rd_own_conf() in dw_pcie_rd_own_conf().
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Check for rd_other_conf() in dw_pcie_rd_other_conf() to make this symmetric
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with the rd_own_conf() checking, and similarly for the write path.
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No functional change intended.
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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---
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drivers/pci/host/pcie-designware.c | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -571,6 +571,9 @@ static int dw_pcie_rd_other_conf(struct
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u64 cpu_addr;
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void __iomem *va_cfg_base;
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+ if (pp->ops->rd_other_conf)
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+ return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
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+
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busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
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PCIE_ATU_FUNC(PCI_FUNC(devfn));
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@@ -605,6 +608,9 @@ static int dw_pcie_wr_other_conf(struct
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u64 cpu_addr;
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void __iomem *va_cfg_base;
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+ if (pp->ops->wr_other_conf)
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+ return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
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+
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busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
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PCIE_ATU_FUNC(PCI_FUNC(devfn));
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@@ -667,9 +673,6 @@ static int dw_pcie_rd_conf(struct pci_bu
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if (bus->number == pp->root_bus_nr)
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return dw_pcie_rd_own_conf(pp, where, size, val);
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- if (pp->ops->rd_other_conf)
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- return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
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-
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return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
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}
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@@ -684,9 +687,6 @@ static int dw_pcie_wr_conf(struct pci_bu
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if (bus->number == pp->root_bus_nr)
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return dw_pcie_wr_own_conf(pp, where, size, val);
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- if (pp->ops->wr_other_conf)
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- return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
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-
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return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
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}
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