4d1656e813
Default kernel doesn't change and stays on 3.18 for now. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46554
264 lines
8.0 KiB
Diff
264 lines
8.0 KiB
Diff
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 7bit
|
|
Subject: [v2,3/5] DT: PCI: qcom: Document PCIe devicetree bindings
|
|
From: Stanimir Varbanov <svarbanov@mm-sol.com>
|
|
X-Patchwork-Id: 6326181
|
|
Message-Id: <1430743338-10441-4-git-send-email-svarbanov@mm-sol.com>
|
|
To: Rob Herring <robh+dt@kernel.org>, Kumar Gala <galak@codeaurora.org>,
|
|
Mark Rutland <mark.rutland@arm.com>,
|
|
Grant Likely <grant.likely@linaro.org>,
|
|
Bjorn Helgaas <bhelgaas@google.com>,
|
|
Kishon Vijay Abraham I <kishon@ti.com>,
|
|
Russell King <linux@arm.linux.org.uk>, Arnd Bergmann <arnd@arndb.de>
|
|
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
|
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
|
|
linux-pci@vger.kernel.org, Mathieu Olivari <mathieu@codeaurora.org>,
|
|
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
|
|
Stanimir Varbanov <svarbanov@mm-sol.com>
|
|
Date: Mon, 4 May 2015 15:42:16 +0300
|
|
|
|
Document Qualcomm PCIe driver devicetree bindings.
|
|
|
|
Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
|
|
|
|
---
|
|
.../devicetree/bindings/pci/qcom,pcie.txt | 231 ++++++++++++++++++++
|
|
1 files changed, 231 insertions(+), 0 deletions(-)
|
|
create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt
|
|
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
|
|
@@ -0,0 +1,231 @@
|
|
+* Qualcomm PCI express root complex
|
|
+
|
|
+- compatible:
|
|
+ Usage: required
|
|
+ Value type: <stringlist>
|
|
+ Definition: Value shall include
|
|
+ - "qcom,pcie-v0" for apq/ipq8064
|
|
+ - "qcom,pcie-v1" for apq8084
|
|
+
|
|
+- reg:
|
|
+ Usage: required
|
|
+ Value type: <prop-encoded-array>
|
|
+ Definition: Register ranges as listed in the reg-names property
|
|
+
|
|
+- reg-names:
|
|
+ Usage: required
|
|
+ Value type: <stringlist>
|
|
+ Definition: Must include the following entries
|
|
+ - "parf" Qualcomm specific registers
|
|
+ - "dbi" Designware PCIe registers
|
|
+ - "elbi" External local bus interface registers
|
|
+ - "config" PCIe configuration space
|
|
+
|
|
+- device_type:
|
|
+ Usage: required
|
|
+ Value type: <string>
|
|
+ Definition: Should be "pci". As specified in designware-pcie.txt
|
|
+
|
|
+- #address-cells:
|
|
+ Usage: required
|
|
+ Value type: <u32>
|
|
+ Definition: Should be set to 3. As specified in designware-pcie.txt
|
|
+
|
|
+- #size-cells:
|
|
+ Usage: required
|
|
+ Value type: <u32>
|
|
+ Definition: Should be set 2. As specified in designware-pcie.txt
|
|
+
|
|
+- ranges:
|
|
+ Usage: required
|
|
+ Value type: <prop-encoded-array>
|
|
+ Definition: As specified in designware-pcie.txt
|
|
+
|
|
+- interrupts:
|
|
+ Usage: required
|
|
+ Value type: <prop-encoded-array>
|
|
+ Definition: MSI interrupt
|
|
+
|
|
+- interrupt-names:
|
|
+ Usage: required
|
|
+ Value type: <stringlist>
|
|
+ Definition: Should contain "msi"
|
|
+
|
|
+- #interrupt-cells:
|
|
+ Usage: required
|
|
+ Value type: <u32>
|
|
+ Definition: Should be 1. As specified in designware-pcie.txt
|
|
+
|
|
+- interrupt-map-mask:
|
|
+ Usage: required
|
|
+ Value type: <prop-encoded-array>
|
|
+ Definition: As specified in designware-pcie.txt
|
|
+
|
|
+- interrupt-map:
|
|
+ Usage: required
|
|
+ Value type: <prop-encoded-array>
|
|
+ Definition: As specified in designware-pcie.txt
|
|
+
|
|
+- clocks:
|
|
+ Usage: required
|
|
+ Value type: <prop-encoded-array>
|
|
+ Definition: List of phandle and clock specifier pairs as listed
|
|
+ in clock-names property
|
|
+
|
|
+- clock-names:
|
|
+ Usage: required
|
|
+ Value type: <stringlist>
|
|
+ Definition: Should contain the following entries
|
|
+ * should be populated for v0 and v1
|
|
+ - "iface" Configuration AHB clock
|
|
+
|
|
+ * should be populated for v0
|
|
+ - "core" Clocks the pcie hw block
|
|
+ - "phy" Clocks the pcie PHY block
|
|
+
|
|
+ * should be populated for v1
|
|
+ - "aux" Auxiliary (AUX) clock
|
|
+ - "bus_master" Master AXI clock
|
|
+ - "bus_slave" Slave AXI clock
|
|
+
|
|
+- resets:
|
|
+ Usage: required
|
|
+ Value type: <prop-encoded-array>
|
|
+ Definition: List of phandle and reset specifier pairs as listed
|
|
+ in reset-names property
|
|
+
|
|
+- reset-names:
|
|
+ Usage: required
|
|
+ Value type: <stringlist>
|
|
+ Definition: Should contain the following entries
|
|
+ * should be populated for v0
|
|
+ - "axi" AXI reset
|
|
+ - "ahb" AHB reset
|
|
+ - "por" POR reset
|
|
+ - "pci" PCI reset
|
|
+ - "phy" PHY reset
|
|
+
|
|
+ * should be populated for v1
|
|
+ - "core" Core reset
|
|
+
|
|
+- power-domains:
|
|
+ Usage: required (for v1 only)
|
|
+ Value type: <prop-encoded-array>
|
|
+ Definition: A phandle and power domain specifier pair to the
|
|
+ power domain which is responsible for collapsing
|
|
+ and restoring power to the peripheral
|
|
+
|
|
+- <name>-supply:
|
|
+ Usage: required
|
|
+ Value type: <phandle>
|
|
+ Definition: List of phandles to the power supply regulator(s)
|
|
+ * should be populated for v0 and v1
|
|
+ - "vdda" core analog power supply
|
|
+
|
|
+ * should be populated for v0
|
|
+ - "vdda_phy" analog power supply for PHY
|
|
+ - "vdda_refclk" analog power supply for IC which generate
|
|
+ reference clock
|
|
+
|
|
+- phys:
|
|
+ Usage: required (for v1 only)
|
|
+ Value type: <phandle>
|
|
+ Definition: List of phandle(s) as listed in phy-names property
|
|
+
|
|
+- phy-names:
|
|
+ Usage: required (for v1 only)
|
|
+ Value type: <stringlist>
|
|
+ Definition: Should contain "pciephy"
|
|
+
|
|
+- <name>-gpio:
|
|
+ Usage: optional
|
|
+ Value type: <prop-encoded-array>
|
|
+ Definition: List of phandle and gpio specifier pairs. Should contain
|
|
+ - "perst" PCIe endpoint reset signal line
|
|
+ - "pewake" PCIe endpoint wake signal line
|
|
+
|
|
+- pinctrl-0:
|
|
+ Usage: required
|
|
+ Value type: <phandle>
|
|
+ Definition: List of phandles pointing at a pin(s) configuration
|
|
+
|
|
+- pinctrl-names
|
|
+ Usage: required
|
|
+ Value type: <stringlist>
|
|
+ Definition: List of names of pinctrl-0 state
|
|
+
|
|
+* Example for v0
|
|
+ pcie0: pci@1b500000 {
|
|
+ compatible = "qcom,pcie-v0";
|
|
+ reg = <0x1b500000 0x1000
|
|
+ 0x1b502000 0x80
|
|
+ 0x1b600000 0x100
|
|
+ 0x0ff00000 0x100000>;
|
|
+ reg-names = "dbi", "elbi", "parf", "config";
|
|
+ device_type = "pci";
|
|
+ linux,pci-domain = <0>;
|
|
+ bus-range = <0x00 0xff>;
|
|
+ num-lanes = <1>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
|
|
+ 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* memory */
|
|
+ interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
|
|
+ interrupt-names = "msi";
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 0x7>;
|
|
+ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
+ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
+ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
+ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
+ clocks = <&gcc PCIE_A_CLK>,
|
|
+ <&gcc PCIE_H_CLK>,
|
|
+ <&gcc PCIE_PHY_CLK>;
|
|
+ clock-names = "core", "iface", "phy";
|
|
+ resets = <&gcc PCIE_ACLK_RESET>,
|
|
+ <&gcc PCIE_HCLK_RESET>,
|
|
+ <&gcc PCIE_POR_RESET>,
|
|
+ <&gcc PCIE_PCI_RESET>,
|
|
+ <&gcc PCIE_PHY_RESET>;
|
|
+ reset-names = "axi", "ahb", "por", "pci", "phy";
|
|
+ };
|
|
+
|
|
+* Example for v1
|
|
+ pcie0@fc520000 {
|
|
+ compatible = "qcom,pcie-v1";
|
|
+ reg = <0xfc520000 0x2000>,
|
|
+ <0xff000000 0x1000>,
|
|
+ <0xff001000 0x1000>,
|
|
+ <0xff002000 0x2000>;
|
|
+ reg-names = "parf", "dbi", "elbi", "config";
|
|
+ device_type = "pci";
|
|
+ linux,pci-domain = <0>;
|
|
+ bus-range = <0x00 0xff>;
|
|
+ num-lanes = <1>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
|
|
+ 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
|
|
+ interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
|
|
+ interrupt-names = "msi";
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 0x7>;
|
|
+ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
+ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
+ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
+ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
+ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
|
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
|
+ <&gcc GCC_PCIE_0_AUX_CLK>;
|
|
+ clock-names = "iface", "master_bus", "slave_bus", "aux";
|
|
+ resets = <&gcc GCC_PCIE_0_BCR>;
|
|
+ reset-names = "core";
|
|
+ power-domains = <&gcc PCIE0_GDSC>;
|
|
+ vdda-supply = <&pma8084_l3>;
|
|
+ phys = <&pciephy0>;
|
|
+ phy-names = "pciephy";
|
|
+ perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
|
|
+ pinctrl-0 = <&pcie0_pins_default>;
|
|
+ pinctrl-names = "default";
|
|
+ };
|