883250014d
All device DTS files in the target set the serial0 property to the same value (*). So, let's move the definitions to the DTSI files. That's also where the kernel defines it (qcom-ipq8064-v1.0.dtsi). * The only exception is ipq8064-db149, which defines "serial0 = &uart2;", but inside a block called "alias" instead of "aliases". It must be assumed that this is broken anyway, so we don't touch it here. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
167 lines
2.4 KiB
Plaintext
167 lines
2.4 KiB
Plaintext
#include "qcom-ipq8064-v1.0.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
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compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
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memory@0 {
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reg = <0x42000000 0x1e000000>;
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device_type = "memory";
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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rsvd@41200000 {
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reg = <0x41200000 0x300000>;
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no-map;
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};
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};
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aliases {
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mdio-gpio0 = &mdio0;
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};
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};
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&adm_dma {
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status = "okay";
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};
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&gsbi4 {
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qcom,mode = <GSBI_PROT_I2C_UART>;
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status = "okay";
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serial@16340000 {
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status = "okay";
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};
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/*
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* The i2c device on gsbi4 should not be enabled.
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* On ipq806x designs gsbi4 i2c is meant for exclusive
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* RPM usage. Turning this on in kernel manifests as
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* i2c failure for the RPM.
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*/
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};
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&gsbi5 {
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qcom,mode = <GSBI_PROT_SPI>;
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status = "okay";
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spi4: spi@1a280000 {
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status = "okay";
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spi-max-frequency = <50000000>;
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pinctrl-0 = <&spi_pins>;
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pinctrl-names = "default";
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cs-gpios = <&qcom_pinmux 20 0>;
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m25p80@0 {
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compatible = "s25fl256s1";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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partitions {
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compatible = "qcom,smem";
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};
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};
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};
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};
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&usb3_0 {
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status = "okay";
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};
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&usb3_1 {
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status = "okay";
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};
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&pcie0 {
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status = "okay";
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};
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&pcie1 {
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status = "okay";
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force_gen1 = <1>;
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};
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&nand_controller {
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status = "okay";
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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nand@0 {
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reg = <0>;
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compatible = "qcom,nandcs";
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nand-ecc-strength = <4>;
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nand-bus-width = <8>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "qcom,smem";
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};
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};
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};
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&mdio0 {
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status = "okay";
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pinctrl-0 = <&mdio0_pins>;
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pinctrl-names = "default";
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phy0: ethernet-phy@0 {
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reg = <0>;
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qca,ar8327-initvals = <
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0x00004 0x7600000 /* PAD0_MODE */
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0x00008 0x1000000 /* PAD5_MODE */
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0x0000c 0x80 /* PAD6_MODE */
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0x000e4 0x6a545 /* MAC_POWER_SEL */
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0x000e0 0xc74164de /* SGMII_CTRL */
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0x0007c 0x4e /* PORT0_STATUS */
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0x00094 0x4e /* PORT6_STATUS */
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>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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};
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii";
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qcom,id = <1>;
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pinctrl-0 = <&rgmii2_pins>;
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pinctrl-names = "default";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&gmac2 {
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status = "okay";
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phy-mode = "sgmii";
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qcom,id = <2>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&sata_phy {
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status = "okay";
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};
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&sata {
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status = "okay";
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};
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