af015f956c
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH SVN-Revision: 29868
76 lines
2.2 KiB
Diff
76 lines
2.2 KiB
Diff
From cfb725275ea25857e8f0e3bf358fff7c84cc787c Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Tue, 22 Nov 2011 13:59:39 +0100
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Subject: [PATCH 12/35] MIPS: ath79: fix a wrong IRQ number
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The Ubiquiti XM board setup code uses an invalid
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IRQ number, because it if above of NR_IRQS. This
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leads to failed 'request_irq' calls:
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ath9k 0000:00:00.0: request_irq failed
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ath9k: probe of 0000:00:00.0 failed with error -22
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Preserve some IRQ numbers for the built-in IRQ
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controller of PCI host controllers in the
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AR71XX/AR724X SoCs, and use the correct IRQ
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number in the board setup code.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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v2: - no changes
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The IRQ controller code is also missing, that will be
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added in a separate patch.
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---
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arch/mips/ath79/mach-ubnt-xm.c | 5 +++--
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arch/mips/include/asm/mach-ath79/irq.h | 6 +++++-
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2 files changed, 8 insertions(+), 3 deletions(-)
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--- a/arch/mips/ath79/mach-ubnt-xm.c
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+++ b/arch/mips/ath79/mach-ubnt-xm.c
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@@ -17,6 +17,8 @@
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#include <linux/ath9k_platform.h>
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#endif /* CONFIG_PCI */
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+#include <asm/mach-ath79/irq.h>
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+
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#include "machtypes.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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@@ -33,7 +35,6 @@
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#define UBNT_XM_KEYS_POLL_INTERVAL 20
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#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
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-#define UBNT_XM_PCI_IRQ 48
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#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
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static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
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@@ -86,7 +87,7 @@ static struct ath9k_platform_data ubnt_x
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static struct ar724x_pci_data ubnt_xm_pci_data[] = {
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{
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- .irq = UBNT_XM_PCI_IRQ,
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+ .irq = ATH79_PCI_IRQ(0),
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.pdata = &ubnt_xm_eeprom_data,
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},
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};
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--- a/arch/mips/include/asm/mach-ath79/irq.h
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+++ b/arch/mips/include/asm/mach-ath79/irq.h
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@@ -10,11 +10,15 @@
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#define __ASM_MACH_ATH79_IRQ_H
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#define MIPS_CPU_IRQ_BASE 0
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-#define NR_IRQS 40
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+#define NR_IRQS 46
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#define ATH79_MISC_IRQ_BASE 8
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#define ATH79_MISC_IRQ_COUNT 32
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+#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
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+#define ATH79_PCI_IRQ_COUNT 6
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+#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
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+
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#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
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#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
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#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
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