cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
69 lines
2.1 KiB
Diff
69 lines
2.1 KiB
Diff
From 74920ba156136a58dd3411c02d429d4f31497dc0 Mon Sep 17 00:00:00 2001
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From: Marc Kleine-Budde <mkl@pengutronix.de>
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Date: Fri, 1 Mar 2019 15:38:05 +0100
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Subject: [PATCH] can: flexcan: flexcan_read_reg_iflag_rx(): optimize reading
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The flexcan IP core has up to 64 mailboxes, each one has a corresponding
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interrupt bit in the iflag1 or iflag2 registers and a mask bit in the
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imask1 or imask2 registers.
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In the timestamp (i.e. non FIFO) mode the driver needs to mask all non RX
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interrupt sources, it uses the precomputed value rx_mask of struct flexcan_priv
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for this.
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In certain use cases, for example the CANFD mode, the contents of the iflag2
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register is completely masked.
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This patch optimizes the flexcan_read_reg_iflag_rx() function by not reading
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the iflag1 or iflag2 register if the contents is masked.
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Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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---
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drivers/net/can/flexcan.c | 28 +++++++++++++++++-----------
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1 file changed, 17 insertions(+), 11 deletions(-)
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--- a/drivers/net/can/flexcan.c
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+++ b/drivers/net/can/flexcan.c
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@@ -779,6 +779,23 @@ static void flexcan_irq_state(struct net
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dev->stats.rx_fifo_errors++;
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}
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+static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask)
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+{
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+ u64 reg = 0;
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+
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+ if (upper_32_bits(mask))
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+ reg = (u64)priv->read(addr - 4) << 32;
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+ if (lower_32_bits(mask))
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+ reg |= priv->read(addr);
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+
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+ return reg & mask;
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+}
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+
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+static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
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+{
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+ return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask);
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+}
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+
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static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
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{
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return container_of(offload, struct flexcan_priv, offload);
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@@ -873,17 +890,6 @@ static struct sk_buff *flexcan_mailbox_r
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return skb;
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}
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-static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
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-{
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- struct flexcan_regs __iomem *regs = priv->regs;
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- u64 iflag;
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-
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- iflag = (u64)priv->read(®s->iflag2) << 32 |
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- priv->read(®s->iflag1);
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-
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- return iflag & priv->rx_mask;
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-}
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-
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static irqreturn_t flexcan_irq(int irq, void *dev_id)
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{
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struct net_device *dev = dev_id;
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