cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
170 lines
5.3 KiB
Diff
170 lines
5.3 KiB
Diff
From 6943ed031ee75f13a950e293f92db68ea2ec2786 Mon Sep 17 00:00:00 2001
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From: Claudiu Manoil <claudiu.manoil@nxp.com>
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Date: Wed, 14 Aug 2019 14:34:47 +0300
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Subject: [PATCH] enetc: Initialize SerDes for SGMII and SXGMII protocols
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ENETC has ethernet MACs capable of SGMII and SXGMII but
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in order to use these protocols some serdes configurations
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need to be performed.
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The serdes is configurable via an internal MDIO bus
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connected to an internal PCS device, all reads/writes are
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performed at address 0.
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This patch basically removes the dependecy on a bootloader
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regarding serdes initialization.
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Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
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Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
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---
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drivers/net/ethernet/freescale/enetc/enetc_hw.h | 17 +++++++
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drivers/net/ethernet/freescale/enetc/enetc_mdio.c | 24 +++++++++
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drivers/net/ethernet/freescale/enetc/enetc_pf.c | 59 +++++++++++++++++++++++
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drivers/net/ethernet/freescale/enetc/enetc_pf.h | 2 +
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4 files changed, 102 insertions(+)
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--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
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+++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
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@@ -221,6 +221,23 @@ enum enetc_bdr_type {TX, RX};
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#define ENETC_PM0_MAXFRM 0x8014
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#define ENETC_SET_TX_MTU(val) ((val) << 16)
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#define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
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+
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+#define ENETC_PM_IMDIO_BASE 0x8030
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+/* PCS registers */
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+#define ENETC_PCS_CR 0x0
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+#define ENETC_PCS_CR_RESET_AN 0x1200
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+#define ENETC_PCS_CR_DEF_VAL 0x0140
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+#define ENETC_PCS_CR_LANE_RESET 0x8000
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+#define ENETC_PCS_DEV_ABILITY 0x04
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+#define ENETC_PCS_DEV_ABILITY_SGMII 0x4001
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+#define ENETC_PCS_DEV_ABILITY_SXGMII 0x5001
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+#define ENETC_PCS_LINK_TIMER1 0x12
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+#define ENETC_PCS_LINK_TIMER1_VAL 0x06a0
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+#define ENETC_PCS_LINK_TIMER2 0x13
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+#define ENETC_PCS_LINK_TIMER2_VAL 0x0003
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+#define ENETC_PCS_IF_MODE 0x14
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+#define ENETC_PCS_IF_MODE_SGMII_AN 0x0003
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+
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#define ENETC_PM0_IF_MODE 0x8300
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#define ENETC_PMO_IFM_RG BIT(2)
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#define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
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--- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
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+++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
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@@ -200,3 +200,27 @@ void enetc_mdio_remove(struct enetc_pf *
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if (pf->mdio)
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mdiobus_unregister(pf->mdio);
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}
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+
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+int enetc_imdio_init(struct enetc_pf *pf)
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+{
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+ struct device *dev = &pf->si->pdev->dev;
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+ struct enetc_mdio_priv *mdio_priv;
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+ struct mii_bus *bus;
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+
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+ bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
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+ if (!bus)
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+ return -ENOMEM;
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+
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+ bus->name = "FSL ENETC internal MDIO Bus";
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+ bus->read = enetc_mdio_read;
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+ bus->write = enetc_mdio_write;
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+ bus->parent = dev;
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+ mdio_priv = bus->priv;
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+ mdio_priv->hw = &pf->si->hw;
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+ mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
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+ snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
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+
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+ pf->imdio = bus;
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+
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+ return 0;
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+}
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--- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c
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+++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c
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@@ -807,6 +807,61 @@ static void enetc_of_put_phy(struct enet
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of_node_put(priv->phy_node);
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}
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+static void enetc_configure_sgmii(struct mii_bus *imdio)
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+{
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+ /* Set to SGMII mode, use AN */
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+ imdio->write(imdio, 0, ENETC_PCS_IF_MODE,
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+ ENETC_PCS_IF_MODE_SGMII_AN);
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+
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+ /* Dev ability - SGMII */
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+ imdio->write(imdio, 0, ENETC_PCS_DEV_ABILITY,
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+ ENETC_PCS_DEV_ABILITY_SGMII);
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+
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+ /* Adjust link timer for SGMII */
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+ imdio->write(imdio, 0, ENETC_PCS_LINK_TIMER1,
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+ ENETC_PCS_LINK_TIMER1_VAL);
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+ imdio->write(imdio, 0, ENETC_PCS_LINK_TIMER2,
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+ ENETC_PCS_LINK_TIMER2_VAL);
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+
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+ /* restart PCS AN */
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+ imdio->write(imdio, 0, ENETC_PCS_CR,
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+ ENETC_PCS_CR_RESET_AN | ENETC_PCS_CR_DEF_VAL);
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+}
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+
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+static void enetc_configure_sxgmii(struct mii_bus *imdio)
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+{
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+ /* Dev ability - SXGMII */
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+ imdio->write(imdio, 0, MII_ADDR_C45 | (MDIO_MMD_VEND2 << 16) |
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+ ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
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+
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+ /* Restart PCS AN */
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+ imdio->write(imdio, 0, MII_ADDR_C45 | (MDIO_MMD_VEND2 << 16) |
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+ ENETC_PCS_CR,
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+ ENETC_PCS_CR_LANE_RESET | ENETC_PCS_CR_RESET_AN);
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+}
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+
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+static int enetc_configure_serdes(struct enetc_ndev_priv *priv)
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+{
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+ struct enetc_pf *pf = enetc_si_priv(priv->si);
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+ int err;
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+
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+ if (priv->if_mode != PHY_INTERFACE_MODE_SGMII &&
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+ priv->if_mode != PHY_INTERFACE_MODE_XGMII)
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+ return 0;
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+
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+ err = enetc_imdio_init(pf);
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+ if (err)
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+ return err;
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+
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+ if (priv->if_mode == PHY_INTERFACE_MODE_SGMII)
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+ enetc_configure_sgmii(pf->imdio);
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+
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+ if (priv->if_mode == PHY_INTERFACE_MODE_XGMII)
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+ enetc_configure_sxgmii(pf->imdio);
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+
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+ return 0;
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+}
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+
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static int enetc_pf_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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@@ -871,6 +926,10 @@ static int enetc_pf_probe(struct pci_dev
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if (err)
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dev_warn(&pdev->dev, "Fallback to PHY-less operation\n");
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+ err = enetc_configure_serdes(priv);
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+ if (err)
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+ dev_warn(&pdev->dev, "Attempted serdes config but failed\n");
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+
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err = register_netdev(ndev);
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if (err)
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goto err_reg_netdev;
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--- a/drivers/net/ethernet/freescale/enetc/enetc_pf.h
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+++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.h
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@@ -44,6 +44,7 @@ struct enetc_pf {
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DECLARE_BITMAP(active_vlans, VLAN_N_VID);
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struct mii_bus *mdio; /* saved for cleanup */
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+ struct mii_bus *imdio;
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};
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int enetc_msg_psi_init(struct enetc_pf *pf);
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@@ -53,3 +54,4 @@ void enetc_msg_handle_rxmsg(struct enetc
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/* MDIO */
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int enetc_mdio_probe(struct enetc_pf *pf);
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void enetc_mdio_remove(struct enetc_pf *pf);
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+int enetc_imdio_init(struct enetc_pf *pf);
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