25ca004f24
bcm47xx misses cpu overwrites for the features of the CPUs used in these SoCs. Instead of manually checking, it is now known at compile time for some options and the compiler is able to remove the checks and optimize the code. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 38974
96 lines
3.0 KiB
Diff
96 lines
3.0 KiB
Diff
From b27da7f1ee034d32e410faf5ab32fc96424a0c62 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Wed, 20 Nov 2013 22:16:43 +0100
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Subject: [PATCH 17/18] add overwrite
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---
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.../asm/mach-bcm47xx/cpu-feature-overrides.h | 82 ++++++++++++++++++++
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1 file changed, 82 insertions(+)
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create mode 100644 arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
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@@ -0,0 +1,82 @@
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+#ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
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+#define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H
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+
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+#define cpu_has_tlb 1
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+#define cpu_has_4kex 1
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+#define cpu_has_3k_cache 0
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+#define cpu_has_4k_cache 1
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+#define cpu_has_tx39_cache 0
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+#define cpu_has_fpu 0
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+#define cpu_has_32fpr 0
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+#define cpu_has_counter 1
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+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
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+#define cpu_has_watch 1
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+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
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+#define cpu_has_watch 0
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+#endif
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+#define cpu_has_divec 1
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+#define cpu_has_vce 0
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+#define cpu_has_cache_cdex_p 0
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+#define cpu_has_cache_cdex_s 0
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+#define cpu_has_prefetch 1
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+#define cpu_has_mcheck 1
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+#define cpu_has_ejtag 1
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+#define cpu_has_llsc 1
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+
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+/* cpu_has_mips16 */
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+#define cpu_has_mdmx 0
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+#define cpu_has_mips3d 0
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+#define cpu_has_rixi 0
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+#define cpu_has_mmips 0
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+#define cpu_has_smartmips 0
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+#define cpu_has_vtag_icache 0
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+/* cpu_has_dc_aliases */
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+#define cpu_has_ic_fills_f_dc 0
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+#define cpu_has_pindexed_dcache 0
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+#define cpu_icache_snoops_remote_store 0
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+
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+#define cpu_has_mips_2 1
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+#define cpu_has_mips_3 0
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+#define cpu_has_mips32r1 1
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+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
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+#define cpu_has_mips32r2 1
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+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
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+#define cpu_has_mips32r2 0
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+#endif
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+#define cpu_has_mips64r1 0
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+#define cpu_has_mips64r2 0
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+
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+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
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+#define cpu_has_dsp 1
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+#define cpu_has_dsp2 1
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+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
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+#define cpu_has_dsp 0
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+#define cpu_has_dsp2 0
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+#endif
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+#define cpu_has_mipsmt 0
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+/* cpu_has_userlocal */
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+
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+#define cpu_has_nofpuex 0
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+#define cpu_has_64bits 0
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+#define cpu_has_64bit_zero_reg 0
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+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
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+#define cpu_has_vint 1
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+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
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+#define cpu_has_vint 0
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+#endif
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+#define cpu_has_veic 0
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+#define cpu_has_inclusive_pcaches 0
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+
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+#if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB)
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+#define cpu_dcache_line_size() 32
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+#define cpu_icache_line_size() 32
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+#define cpu_has_perf_cntr_intr_bit 1
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+#elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA)
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+#define cpu_dcache_line_size() 16
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+#define cpu_icache_line_size() 16
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+#define cpu_has_perf_cntr_intr_bit 0
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+#endif
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+#define cpu_scache_line_size() 0
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+#define cpu_has_vz 0
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+
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+#endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
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