3c1f6e358d
Patches are generated using the "format-patch" command from the following location: *https://www.codeaurora.org/cgit/quic/kernel/galak-msm/log/?h=apq_ipq_base *rev=0771849495b4128cac2faf7d49c85c729fc48b20 Patches numbered 76/77/102/103 have already been integrated in 3.14.12, so they're not in this list. All these patches are either integrated are pending integration into kernel.org, therefore these patches should go away once the kernel gets upgraded to 3.16. Support is currently limited to AP148 board but can be extended to other platforms in the future. These changes do not cover ethernet connectivity. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 42334
79 lines
2.4 KiB
Diff
79 lines
2.4 KiB
Diff
From 085d4b834dfced8580aab74707e30699b63e7c36 Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Wed, 29 Jan 2014 17:01:37 -0600
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Subject: [PATCH 006/182] clocksource: qcom: split building of legacy vs
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multiplatform support
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The majority of the clocksource code for the Qualcomm platform is shared
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between newer (multiplatform) and older platforms. However there is a bit
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of code that isn't, so only build it for the appropriate config.
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Acked-by: Olof Johansson <olof@lixom.net>
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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drivers/clocksource/qcom-timer.c | 23 ++++++++++++-----------
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1 file changed, 12 insertions(+), 11 deletions(-)
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diff --git a/drivers/clocksource/qcom-timer.c b/drivers/clocksource/qcom-timer.c
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index dca829e..e807acf 100644
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--- a/drivers/clocksource/qcom-timer.c
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+++ b/drivers/clocksource/qcom-timer.c
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@@ -106,15 +106,6 @@ static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
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return readl_relaxed(source_base + TIMER_COUNT_VAL);
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}
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-static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
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-{
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- /*
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- * Shift timer count down by a constant due to unreliable lower bits
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- * on some targets.
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- */
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- return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
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-}
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-
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static struct clocksource msm_clocksource = {
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.name = "dg_timer",
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.rating = 300,
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@@ -228,7 +219,7 @@ err:
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sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
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}
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-#ifdef CONFIG_OF
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+#ifdef CONFIG_ARCH_QCOM
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static void __init msm_dt_timer_init(struct device_node *np)
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{
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u32 freq;
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@@ -281,7 +272,7 @@ static void __init msm_dt_timer_init(struct device_node *np)
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}
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CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
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CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
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-#endif
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+#else
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static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
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u32 sts)
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@@ -301,6 +292,15 @@ static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
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return 0;
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}
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+static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
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+{
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+ /*
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+ * Shift timer count down by a constant due to unreliable lower bits
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+ * on some targets.
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+ */
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+ return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
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+}
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+
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void __init msm7x01_timer_init(void)
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{
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struct clocksource *cs = &msm_clocksource;
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@@ -327,3 +327,4 @@ void __init qsd8x50_timer_init(void)
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return;
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msm_timer_init(19200000 / 4, 32, 7, false);
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}
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+#endif
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--
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1.7.10.4
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