f07e572f64
bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G bcm2710: boot tested on RPi 3B v1.2 bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
55 lines
1.9 KiB
Diff
55 lines
1.9 KiB
Diff
From 16349a9b271d331a496a482f46f41a3e1db56891 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Thu, 16 Jul 2020 12:02:47 +0100
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Subject: [PATCH] drm/vc4: Add DRM_MODE_FLAG_DBLCLK support to
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vc4-fkms
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480i and several other modes use DRM_MODE_FLAG_DBLCLK and pixel
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replication.
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Add in flags for that so that FKMS can select CEA modes 6 & 7.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_firmware_kms.c | 11 ++++++++++-
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1 file changed, 10 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c
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+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c
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@@ -158,6 +158,8 @@ struct set_timings {
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#define TIMINGS_FLAGS_RGB_LIMITED BIT(8)
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/* DVI monitor, therefore disable infoframes. Not set corresponds to HDMI. */
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#define TIMINGS_FLAGS_DVI BIT(9)
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+/* Double clock */
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+#define TIMINGS_FLAGS_DBL_CLK BIT(10)
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};
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struct mailbox_set_mode {
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@@ -946,6 +948,8 @@ static void vc4_crtc_mode_set_nofb(struc
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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mb.timings.flags |= TIMINGS_FLAGS_INTERLACE;
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+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
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+ mb.timings.flags |= TIMINGS_FLAGS_DBL_CLK;
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mb.timings.video_id_code = frame.avi.video_code;
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@@ -1104,11 +1108,16 @@ vc4_crtc_mode_valid(struct drm_crtc *crt
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*/
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if (fkms->bcm2711 &&
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(vc4_crtc->display_number == 2 || vc4_crtc->display_number == 7) &&
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+ !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
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((mode->hdisplay | /* active */
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(mode->hsync_start - mode->hdisplay) | /* front porch */
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(mode->hsync_end - mode->hsync_start) | /* sync pulse */
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- (mode->htotal - mode->hsync_end)) & 1)) /* back porch */
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+ (mode->htotal - mode->hsync_end)) & 1)) /* back porch */ {
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+ DRM_DEBUG_KMS("[CRTC:%d] Odd timing rejected %u %u %u %u.\n",
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+ crtc->base.id, mode->hdisplay, mode->hsync_start,
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+ mode->hsync_end, mode->htotal);
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return MODE_H_ILLEGAL;
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+ }
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return MODE_OK;
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}
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