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Openwrt/target/linux/bcm27xx/patches-5.4/950-0406-overlays-Add-ssd1306-spi-ssh1106-spi-ssd-1351-spi.patch
Álvaro Fernández Rojas f07e572f64 bcm27xx: import latest patches from the RPi foundation 
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2021-02-18 23:42:32 +01:00

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From fe90ee51b283f7cbbce9980b76b3da8b31d39c60 Mon Sep 17 00:00:00 2001
From: MikeDK <m.kaplan@evva.com>
Date: Fri, 31 Jan 2020 10:57:21 +0100
Subject: [PATCH] overlays: Add ssd1306-spi, ssh1106-spi, ssd-1351-spi
Add overlays for SSD1306, SH1106 and SSD1351 based OLED displays.
SH1106 is present in many 1.3 inch OLEDs and SSD1351 is present in
1.5 inch RGB OLEDs from AliExpress.
This will load the staging fbtft drivers.
Signed-off-by: Michael Kaplan <m.kaplan@evva.com>
---
arch/arm/boot/dts/overlays/Makefile | 3 +
arch/arm/boot/dts/overlays/README | 35 ++++++++
.../boot/dts/overlays/sh1106-spi-overlay.dts | 84 +++++++++++++++++++
.../boot/dts/overlays/ssd1306-spi-overlay.dts | 84 +++++++++++++++++++
.../boot/dts/overlays/ssd1351-spi-overlay.dts | 83 ++++++++++++++++++
5 files changed, 289 insertions(+)
create mode 100644 arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts
create mode 100644 arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts
create mode 100644 arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts
--- a/arch/arm/boot/dts/overlays/Makefile
+++ b/arch/arm/boot/dts/overlays/Makefile
@@ -145,6 +145,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
sdhost.dtbo \
sdio.dtbo \
sdtweak.dtbo \
+ sh1106-spi.dtbo \
smi.dtbo \
smi-dev.dtbo \
smi-nand.dtbo \
@@ -168,6 +169,8 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
spi6-1cs.dtbo \
spi6-2cs.dtbo \
ssd1306.dtbo \
+ ssd1306-spi.dtbo \
+ ssd1351-spi.dtbo \
superaudioboard.dtbo \
sx150x.dtbo \
tc358743.dtbo \
--- a/arch/arm/boot/dts/overlays/README
+++ b/arch/arm/boot/dts/overlays/README
@@ -2145,6 +2145,18 @@ Params: overclock_50 Clock (i
(default on)
+Name: sh1106-spi
+Info: Overlay for SH1106 OLED via SPI using fbtft staging driver.
+Load: dtoverlay=sh1106-spi,<param>=<val>
+Params: speed SPI bus speed (default 4000000)
+ rotate Display rotation (0, 90, 180 or 270; default 0)
+ fps Delay between frame updates (default 25)
+ debug Debug output level (0-7; default 0)
+ dc_pin GPIO pin for D/C (default 24)
+ reset_pin GPIO pin for RESET (default 25)
+ height Display height (32 or 64; default 64)
+
+
Name: smi
Info: Enables the Secondary Memory Interface peripheral. Uses GPIOs 2-25!
Load: dtoverlay=smi
@@ -2428,6 +2440,29 @@ Params: address Location
https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf
+Name: ssd1306-spi
+Info: Overlay for SSD1306 OLED via SPI using fbtft staging driver.
+Load: dtoverlay=ssd1306-spi,<param>=<val>
+Params: speed SPI bus speed (default 10000000)
+ rotate Display rotation (0, 90, 180 or 270; default 0)
+ fps Delay between frame updates (default 25)
+ debug Debug output level (0-7; default 0)
+ dc_pin GPIO pin for D/C (default 24)
+ reset_pin GPIO pin for RESET (default 25)
+ height Display height (32 or 64; default 64)
+
+
+Name: ssd1351-spi
+Info: Overlay for SSD1351 OLED via SPI using fbtft staging driver.
+Load: dtoverlay=ssd1351-spi,<param>=<val>
+Params: speed SPI bus speed (default 4500000)
+ rotate Display rotation (0, 90, 180 or 270; default 0)
+ fps Delay between frame updates (default 25)
+ debug Debug output level (0-7; default 0)
+ dc_pin GPIO pin for D/C (default 24)
+ reset_pin GPIO pin for RESET (default 25)
+
+
Name: superaudioboard
Info: Configures the SuperAudioBoard sound card
Load: dtoverlay=superaudioboard,<param>=<val>
--- /dev/null
+++ b/arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts
@@ -0,0 +1,84 @@
+/*
+ * Device Tree overlay for SH1106 based SPI OLED display
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "brcm,bcm2835";
+
+ fragment@0 {
+ target = <&spi0>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target = <&spidev0>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ fragment@2 {
+ target = <&spidev1>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ fragment@3 {
+ target = <&gpio>;
+ __overlay__ {
+ sh1106_pins: sh1106_pins {
+ brcm,pins = <25 24>;
+ brcm,function = <1 1>; /* out out */
+ };
+ };
+ };
+
+ fragment@4 {
+ target = <&spi0>;
+ __overlay__ {
+ /* needed to avoid dtc warning */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sh1106: sh1106@0{
+ compatible = "sinowealth,sh1106";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sh1106_pins>;
+
+ spi-max-frequency = <4000000>;
+ bgr = <0>;
+ bpp = <1>;
+ rotate = <0>;
+ fps = <25>;
+ buswidth = <8>;
+ reset-gpios = <&gpio 25 0>;
+ dc-gpios = <&gpio 24 0>;
+ debug = <0>;
+
+ sinowealth,height = <64>;
+ sinowealth,width = <128>;
+ sinowealth,page-offset = <0>;
+ };
+ };
+ };
+
+ __overrides__ {
+ speed = <&sh1106>,"spi-max-frequency:0";
+ rotate = <&sh1106>,"rotate:0";
+ fps = <&sh1106>,"fps:0";
+ debug = <&sh1106>,"debug:0";
+ dc_pin = <&sh1106>,"dc-gpios:4",
+ <&sh1106_pins>,"brcm,pins:4";
+ reset_pin = <&sh1106>,"reset-gpios:4",
+ <&sh1106_pins>,"brcm,pins:0";
+ height = <&sh1106>,"sinowealth,height:0";
+ };
+};
--- /dev/null
+++ b/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts
@@ -0,0 +1,84 @@
+/*
+ * Device Tree overlay for SSD1306 based SPI OLED display
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "brcm,bcm2835";
+
+ fragment@0 {
+ target = <&spi0>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target = <&spidev0>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ fragment@2 {
+ target = <&spidev1>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ fragment@3 {
+ target = <&gpio>;
+ __overlay__ {
+ ssd1306_pins: ssd1306_pins {
+ brcm,pins = <25 24>;
+ brcm,function = <1 1>; /* out out */
+ };
+ };
+ };
+
+ fragment@4 {
+ target = <&spi0>;
+ __overlay__ {
+ /* needed to avoid dtc warning */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ssd1306: ssd1306@0{
+ compatible = "solomon,ssd1306";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ssd1306_pins>;
+
+ spi-max-frequency = <10000000>;
+ bgr = <0>;
+ bpp = <1>;
+ rotate = <0>;
+ fps = <25>;
+ buswidth = <8>;
+ reset-gpios = <&gpio 25 0>;
+ dc-gpios = <&gpio 24 0>;
+ debug = <0>;
+
+ solomon,height = <64>;
+ solomon,width = <128>;
+ solomon,page-offset = <0>;
+ };
+ };
+ };
+
+ __overrides__ {
+ speed = <&ssd1306>,"spi-max-frequency:0";
+ rotate = <&ssd1306>,"rotate:0";
+ fps = <&ssd1306>,"fps:0";
+ debug = <&ssd1306>,"debug:0";
+ dc_pin = <&ssd1306>,"dc-gpios:4",
+ <&ssd1306_pins>,"brcm,pins:4";
+ reset_pin = <&ssd1306>,"reset-gpios:4",
+ <&ssd1306_pins>,"brcm,pins:0";
+ height = <&ssd1306>,"solomon,height:0";
+ };
+};
--- /dev/null
+++ b/arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts
@@ -0,0 +1,83 @@
+/*
+ * Device Tree overlay for SSD1351 based SPI OLED display
+ *
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "brcm,bcm2835";
+
+ fragment@0 {
+ target = <&spi0>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment@1 {
+ target = <&spidev0>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ fragment@2 {
+ target = <&spidev1>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+ fragment@3 {
+ target = <&gpio>;
+ __overlay__ {
+ ssd1351_pins: ssd1351_pins {
+ brcm,pins = <25 24>;
+ brcm,function = <1 1>; /* out out */
+ };
+ };
+ };
+
+ fragment@4 {
+ target = <&spi0>;
+ __overlay__ {
+ /* needed to avoid dtc warning */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ssd1351: ssd1351@0{
+ compatible = "solomon,ssd1351";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ssd1351_pins>;
+
+ spi-max-frequency = <4500000>;
+ bgr = <0>;
+ bpp = <16>;
+ rotate = <0>;
+ fps = <25>;
+ buswidth = <8>;
+ reset-gpios = <&gpio 25 0>;
+ dc-gpios = <&gpio 24 0>;
+ debug = <0>;
+
+ solomon,height = <128>;
+ solomon,width = <128>;
+ solomon,page-offset = <0>;
+ };
+ };
+ };
+
+ __overrides__ {
+ speed = <&ssd1351>,"spi-max-frequency:0";
+ rotate = <&ssd1351>,"rotate:0";
+ fps = <&ssd1351>,"fps:0";
+ debug = <&ssd1351>,"debug:0";
+ dc_pin = <&ssd1351>,"dc-gpios:4",
+ <&ssd1351_pins>,"brcm,pins:4";
+ reset_pin = <&ssd1351>,"reset-gpios:4",
+ <&ssd1351_pins>,"brcm,pins:0";
+ };
+};
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