f07e572f64
bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G bcm2710: boot tested on RPi 3B v1.2 bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
32 lines
1.2 KiB
Diff
32 lines
1.2 KiB
Diff
From e9d49d1b54bb1f202ac8d4a42c5ebb9a9237da17 Mon Sep 17 00:00:00 2001
|
|
From: Dave Stevenson <dave.stevenson@raspberrypi.org>
|
|
Date: Wed, 31 Oct 2018 14:56:59 +0000
|
|
Subject: [PATCH] media: tc358743: Increase FIFO level to 374.
|
|
|
|
The existing fixed value of 16 worked for UYVY 720P60 over
|
|
2 lanes at 594MHz, or UYVY 1080P60 over 4 lanes. (RGB888
|
|
1080P60 needs 6 lanes at 594MHz).
|
|
It doesn't allow for lower resolutions to work as the FIFO
|
|
underflows.
|
|
|
|
374 is required for 1080P24-30 UYVY over 2 lanes @ 972Mbit/s, but
|
|
>374 means that the FIFO underflows on 1080P50 UYVY over 2 lanes
|
|
@ 972Mbit/s.
|
|
|
|
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
|
|
---
|
|
drivers/media/i2c/tc358743.c | 2 +-
|
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
|
|
--- a/drivers/media/i2c/tc358743.c
|
|
+++ b/drivers/media/i2c/tc358743.c
|
|
@@ -1949,7 +1949,7 @@ static int tc358743_probe_of(struct tc35
|
|
state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
|
|
state->pdata.enable_hdcp = false;
|
|
/* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
|
|
- state->pdata.fifo_level = 16;
|
|
+ state->pdata.fifo_level = 374;
|
|
/*
|
|
* The PLL input clock is obtained by dividing refclk by pll_prd.
|
|
* It must be between 6 MHz and 40 MHz, lower frequency is better.
|