196 lines
4.9 KiB
C
196 lines
4.9 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2005 infineon
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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*/
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#ifndef _IFXMIPS_DMA_H__
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#define _IFXMIPS_DMA_H__
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#define RCV_INT 1
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#define TX_BUF_FULL_INT 2
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#define TRANSMIT_CPT_INT 4
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#define IFXMIPS_DMA_CH_ON 1
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#define IFXMIPS_DMA_CH_OFF 0
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#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100
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enum attr_t{
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TX = 0,
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RX = 1,
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RESERVED = 2,
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DEFAULT = 3,
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};
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#define DMA_OWN 1
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#define CPU_OWN 0
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#define DMA_MAJOR 250
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#define DMA_DESC_OWN_CPU 0x0
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#define DMA_DESC_OWN_DMA 0x80000000
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#define DMA_DESC_CPT_SET 0x40000000
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#define DMA_DESC_SOP_SET 0x20000000
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#define DMA_DESC_EOP_SET 0x10000000
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#define MISCFG_MASK 0x40
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#define RDERR_MASK 0x20
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#define CHOFF_MASK 0x10
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#define DESCPT_MASK 0x8
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#define DUR_MASK 0x4
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#define EOP_MASK 0x2
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#define DMA_DROP_MASK (1<<31)
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#define IFXMIPS_DMA_RX -1
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#define IFXMIPS_DMA_TX 1
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struct dma_chan_map {
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const char *dev_name;
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enum attr_t dir;
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int pri;
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int irq;
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int rel_chan_no;
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};
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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struct rx_desc {
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u32 data_length:16;
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volatile u32 reserved:7;
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volatile u32 byte_offset:2;
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volatile u32 Burst_length_offset:3;
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volatile u32 EoP:1;
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volatile u32 Res:1;
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volatile u32 C:1;
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volatile u32 OWN:1;
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volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
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};
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struct tx_desc {
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volatile u32 data_length:16;
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volatile u32 reserved1:7;
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volatile u32 byte_offset:5;
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volatile u32 EoP:1;
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volatile u32 SoP:1;
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volatile u32 C:1;
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volatile u32 OWN:1;
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volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
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};
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#else /* BIG */
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struct rx_desc {
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union {
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struct {
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volatile u32 OWN:1;
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volatile u32 C:1;
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volatile u32 SoP:1;
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volatile u32 EoP:1;
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volatile u32 Burst_length_offset:3;
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volatile u32 byte_offset:2;
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volatile u32 reserve:7;
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volatile u32 data_length:16;
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} field;
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volatile u32 word;
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} status;
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volatile u32 Data_Pointer;
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};
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struct tx_desc {
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union {
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struct {
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volatile u32 OWN:1;
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volatile u32 C:1;
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volatile u32 SoP:1;
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volatile u32 EoP:1;
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volatile u32 byte_offset:5;
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volatile u32 reserved:7;
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volatile u32 data_length:16;
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} field;
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volatile u32 word;
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} status;
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volatile u32 Data_Pointer;
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};
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#endif /* ENDIAN */
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struct dma_channel_info {
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/* relative channel number */
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int rel_chan_no;
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/* class for this channel for QoS */
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int pri;
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/* specify byte_offset */
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int byte_offset;
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/* direction */
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int dir;
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/* irq number */
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int irq;
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/* descriptor parameter */
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int desc_base;
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int desc_len;
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int curr_desc;
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int prev_desc; /* only used if it is a tx channel*/
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/* weight setting for WFQ algorithm*/
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int weight;
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int default_weight;
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int packet_size;
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int burst_len;
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/* on or off of this channel */
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int control;
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/* optional information for the upper layer devices */
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#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
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void *opt[64];
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#else
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void *opt[25];
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#endif
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/* Pointer to the peripheral device who is using this channel */
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void *dma_dev;
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/* channel operations */
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void (*open)(struct dma_channel_info *pCh);
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void (*close)(struct dma_channel_info *pCh);
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void (*reset)(struct dma_channel_info *pCh);
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void (*enable_irq)(struct dma_channel_info *pCh);
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void (*disable_irq)(struct dma_channel_info *pCh);
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};
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struct dma_device_info {
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/* device name of this peripheral */
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char device_name[15];
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int reserved;
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int tx_burst_len;
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int rx_burst_len;
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int default_weight;
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int current_tx_chan;
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int current_rx_chan;
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int num_tx_chan;
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int num_rx_chan;
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int max_rx_chan_num;
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int max_tx_chan_num;
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struct dma_channel_info *tx_chan[20];
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struct dma_channel_info *rx_chan[20];
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/*functions, optional*/
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u8 *(*buffer_alloc)(int len, int *offset, void **opt);
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void (*buffer_free)(u8 *dataptr, void *opt);
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int (*intr_handler)(struct dma_device_info *info, int status);
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void *priv; /* used by peripheral driver only */
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};
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struct dma_device_info *dma_device_reserve(char *dev_name);
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void dma_device_release(struct dma_device_info *dev);
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void dma_device_register(struct dma_device_info *info);
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void dma_device_unregister(struct dma_device_info *info);
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int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt);
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int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len,
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void *opt);
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#endif
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