d7a28e8ed2
This tidies up the ethernet node in mt7620 DTS files by: - removing unnecessary status as it is not disabled - reordering properties consistently - adding empty lines to enhance readability This should make comparison and reviewing new PRs based on C/P easier. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
128 lines
1.7 KiB
Plaintext
128 lines
1.7 KiB
Plaintext
/dts-v1/;
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#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "ralink,mt7620a-evb", "ralink,mt7620a-soc";
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model = "Ralink MT7620a + MT7610e evaluation board";
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keys {
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compatible = "gpio-keys";
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s2 {
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label = "S2";
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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s3 {
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label = "S3";
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_1>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x50000 0x7b0000>;
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};
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};
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};
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};
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&state_default {
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gpio {
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groups = "i2c", "uartf";
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function = "gpio";
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
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mediatek,portmap = "llllw";
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port@4 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <&phy4>;
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};
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port@5 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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};
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mdio-bus {
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status = "okay";
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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phy-mode = "rgmii";
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};
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};
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};
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&gsw {
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mediatek,port4 = "gmac";
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};
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&sdhci {
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status = "okay";
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};
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&pcie {
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status = "okay";
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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