420 lines
9.7 KiB
C
420 lines
9.7 KiB
C
/*
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* Atheros AR71xx SoC specific interrupt handling
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
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#ifdef CONFIG_PCI
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static void ar71xx_pci_irq_dispatch(void)
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{
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u32 pending;
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pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
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ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
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if (pending & PCI_INT_DEV0)
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do_IRQ(AR71XX_PCI_IRQ_DEV0);
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else if (pending & PCI_INT_DEV1)
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do_IRQ(AR71XX_PCI_IRQ_DEV1);
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else if (pending & PCI_INT_DEV2)
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do_IRQ(AR71XX_PCI_IRQ_DEV2);
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else if (pending & PCI_INT_CORE)
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do_IRQ(AR71XX_PCI_IRQ_CORE);
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else
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spurious_interrupt();
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}
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static void ar71xx_pci_irq_unmask(unsigned int irq)
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{
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irq -= AR71XX_PCI_IRQ_BASE;
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ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
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ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
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}
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static void ar71xx_pci_irq_mask(unsigned int irq)
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{
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irq -= AR71XX_PCI_IRQ_BASE;
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ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
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ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
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}
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static struct irq_chip ar71xx_pci_irq_chip = {
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.name = "AR71XX PCI ",
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.mask = ar71xx_pci_irq_mask,
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.unmask = ar71xx_pci_irq_unmask,
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.mask_ack = ar71xx_pci_irq_mask,
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};
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static struct irqaction ar71xx_pci_irqaction = {
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.handler = no_action,
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.name = "cascade [AR71XX PCI]",
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};
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static void __init ar71xx_pci_irq_init(void)
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{
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int i;
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ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
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ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
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ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
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for (i = AR71XX_PCI_IRQ_BASE;
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i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
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handle_level_irq);
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}
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setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
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}
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static void ar724x_pci_irq_dispatch(void)
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{
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u32 pending;
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pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
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ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
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if (pending & AR724X_PCI_INT_DEV0)
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do_IRQ(AR71XX_PCI_IRQ_DEV0);
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else
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spurious_interrupt();
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}
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static void ar724x_pci_irq_unmask(unsigned int irq)
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{
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switch (irq) {
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case AR71XX_PCI_IRQ_DEV0:
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irq -= AR71XX_PCI_IRQ_BASE;
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ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
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ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
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AR724X_PCI_INT_DEV0);
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/* flush write */
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ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
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}
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}
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static void ar724x_pci_irq_mask(unsigned int irq)
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{
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switch (irq) {
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case AR71XX_PCI_IRQ_DEV0:
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irq -= AR71XX_PCI_IRQ_BASE;
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ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
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ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
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~AR724X_PCI_INT_DEV0);
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/* flush write */
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ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
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ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
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ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
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AR724X_PCI_INT_DEV0);
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/* flush write */
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ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
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}
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}
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static struct irq_chip ar724x_pci_irq_chip = {
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.name = "AR724X PCI ",
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.mask = ar724x_pci_irq_mask,
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.unmask = ar724x_pci_irq_unmask,
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.mask_ack = ar724x_pci_irq_mask,
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};
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static struct irqaction ar724x_pci_irqaction = {
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.handler = no_action,
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.name = "cascade [AR724X PCI]",
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};
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static void __init ar724x_pci_irq_init(void)
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{
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int i;
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ar71xx_ip2_irq_handler = ar724x_pci_irq_dispatch;
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ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
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ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
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for (i = AR71XX_PCI_IRQ_BASE;
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i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
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handle_level_irq);
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}
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setup_irq(AR71XX_CPU_IRQ_PCI, &ar724x_pci_irqaction);
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}
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#else
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static inline void ar71xx_pci_irq_init(void) {};
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static inline void ar724x_pci_irq_init(void) {};
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#endif /* CONFIG_PCI */
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static void ar71xx_gpio_irq_dispatch(void)
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{
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u32 pending;
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pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
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& ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
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if (pending)
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do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
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else
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spurious_interrupt();
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}
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static void ar71xx_gpio_irq_unmask(unsigned int irq)
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{
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irq -= AR71XX_GPIO_IRQ_BASE;
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ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
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ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
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/* flush write */
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ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
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}
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static void ar71xx_gpio_irq_mask(unsigned int irq)
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{
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irq -= AR71XX_GPIO_IRQ_BASE;
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ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
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ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
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/* flush write */
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ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
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}
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#if 0
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static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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/* TODO: implement */
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return 0;
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}
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#else
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#define ar71xx_gpio_irq_set_type NULL
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#endif
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static struct irq_chip ar71xx_gpio_irq_chip = {
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.name = "AR71XX GPIO",
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.unmask = ar71xx_gpio_irq_unmask,
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.mask = ar71xx_gpio_irq_mask,
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.mask_ack = ar71xx_gpio_irq_mask,
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.set_type = ar71xx_gpio_irq_set_type,
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};
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static struct irqaction ar71xx_gpio_irqaction = {
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.handler = no_action,
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.name = "cascade [AR71XX GPIO]",
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};
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#define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
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#define GPIO_INT_ALL 0xffff
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static void __init ar71xx_gpio_irq_init(void)
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{
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int i;
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ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
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ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
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/* setup type of all GPIO interrupts to level sensitive */
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ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
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/* setup polarity of all GPIO interrupts to active high */
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ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
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for (i = AR71XX_GPIO_IRQ_BASE;
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i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
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irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
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set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
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handle_level_irq);
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}
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setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
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}
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static void ar71xx_misc_irq_dispatch(void)
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{
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u32 pending;
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pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
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& ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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if (pending & MISC_INT_UART)
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do_IRQ(AR71XX_MISC_IRQ_UART);
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else if (pending & MISC_INT_DMA)
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do_IRQ(AR71XX_MISC_IRQ_DMA);
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else if (pending & MISC_INT_PERFC)
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do_IRQ(AR71XX_MISC_IRQ_PERFC);
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else if (pending & MISC_INT_TIMER)
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do_IRQ(AR71XX_MISC_IRQ_TIMER);
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else if (pending & MISC_INT_OHCI)
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do_IRQ(AR71XX_MISC_IRQ_OHCI);
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else if (pending & MISC_INT_ERROR)
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do_IRQ(AR71XX_MISC_IRQ_ERROR);
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else if (pending & MISC_INT_GPIO)
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ar71xx_gpio_irq_dispatch();
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else if (pending & MISC_INT_WDOG)
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do_IRQ(AR71XX_MISC_IRQ_WDOG);
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else
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spurious_interrupt();
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}
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static void ar71xx_misc_irq_unmask(unsigned int irq)
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{
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irq -= AR71XX_MISC_IRQ_BASE;
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar71xx_misc_irq_mask(unsigned int irq)
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{
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irq -= AR71XX_MISC_IRQ_BASE;
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar724x_misc_irq_ack(unsigned int irq)
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{
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irq -= AR71XX_MISC_IRQ_BASE;
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS,
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static struct irq_chip ar71xx_misc_irq_chip = {
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.name = "AR71XX MISC",
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.unmask = ar71xx_misc_irq_unmask,
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.mask = ar71xx_misc_irq_mask,
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};
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static struct irqaction ar71xx_misc_irqaction = {
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.handler = no_action,
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.name = "cascade [AR71XX MISC]",
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};
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static void __init ar71xx_misc_irq_init(void)
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{
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int i;
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
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if (ar71xx_soc == AR71XX_SOC_AR7240)
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ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
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else
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ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
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for (i = AR71XX_MISC_IRQ_BASE;
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i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
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handle_level_irq);
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}
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setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
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}
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static void ar913x_wmac_irq_dispatch(void)
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{
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do_IRQ(AR71XX_CPU_IRQ_WMAC);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP7)
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do_IRQ(AR71XX_CPU_IRQ_TIMER);
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else if (pending & STATUSF_IP2)
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ar71xx_ip2_irq_handler();
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else if (pending & STATUSF_IP4)
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do_IRQ(AR71XX_CPU_IRQ_GE0);
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else if (pending & STATUSF_IP5)
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do_IRQ(AR71XX_CPU_IRQ_GE1);
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else if (pending & STATUSF_IP3)
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do_IRQ(AR71XX_CPU_IRQ_USB);
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else if (pending & STATUSF_IP6)
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ar71xx_misc_irq_dispatch();
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else
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spurious_interrupt();
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}
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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ar71xx_misc_irq_init();
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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ar71xx_pci_irq_init();
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break;
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case AR71XX_SOC_AR7240:
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ar724x_pci_irq_init();
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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ar71xx_ip2_irq_handler = ar913x_wmac_irq_dispatch;
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break;
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default:
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BUG();
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}
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ar71xx_gpio_irq_init();
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}
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