6b775f4517
This change cherry-picks the following 3 changes from linux-next: *fb7737 hwspinlock/core: add device tree support *19a0f6 hwspinlock: qcom: Add support for Qualcomm HW Mutex block *bd5717 hwspinlock: qcom: Correct msb in regmap_field We're also adding a patch to add the hardware spinlock device nodes on IPQ806x platforms (033-soc-qcom-Add-sfbp-device-to-IPQ806x-dts.patch). Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46655
81 lines
2.3 KiB
Diff
81 lines
2.3 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -364,15 +364,21 @@
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clocks = <&gcc PCIE_A_CLK>,
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<&gcc PCIE_H_CLK>,
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- <&gcc PCIE_PHY_CLK>;
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- clock-names = "core", "iface", "phy";
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+ <&gcc PCIE_PHY_CLK>,
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+ <&gcc PCIE_AUX_CLK>,
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+ <&gcc PCIE_ALT_REF_CLK>;
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+ clock-names = "core", "iface", "phy", "aux", "ref";
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+
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+ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
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+ assigned-clock-rates = <100000000>;
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resets = <&gcc PCIE_ACLK_RESET>,
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<&gcc PCIE_HCLK_RESET>,
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<&gcc PCIE_POR_RESET>,
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<&gcc PCIE_PCI_RESET>,
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- <&gcc PCIE_PHY_RESET>;
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- reset-names = "axi", "ahb", "por", "pci", "phy";
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+ <&gcc PCIE_PHY_RESET>,
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+ <&gcc PCIE_EXT_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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status = "disabled";
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};
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@@ -405,15 +411,21 @@
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clocks = <&gcc PCIE_1_A_CLK>,
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<&gcc PCIE_1_H_CLK>,
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- <&gcc PCIE_1_PHY_CLK>;
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- clock-names = "core", "iface", "phy";
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+ <&gcc PCIE_1_PHY_CLK>,
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+ <&gcc PCIE_1_AUX_CLK>,
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+ <&gcc PCIE_1_ALT_REF_CLK>;
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+ clock-names = "core", "iface", "phy", "aux", "ref";
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+
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+ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
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+ assigned-clock-rates = <100000000>;
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resets = <&gcc PCIE_1_ACLK_RESET>,
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<&gcc PCIE_1_HCLK_RESET>,
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<&gcc PCIE_1_POR_RESET>,
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<&gcc PCIE_1_PCI_RESET>,
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- <&gcc PCIE_1_PHY_RESET>;
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- reset-names = "axi", "ahb", "por", "pci", "phy";
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+ <&gcc PCIE_1_PHY_RESET>,
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+ <&gcc PCIE_1_EXT_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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status = "disabled";
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};
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@@ -446,15 +458,21 @@
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clocks = <&gcc PCIE_2_A_CLK>,
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<&gcc PCIE_2_H_CLK>,
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- <&gcc PCIE_2_PHY_CLK>;
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- clock-names = "core", "iface", "phy";
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+ <&gcc PCIE_2_PHY_CLK>,
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+ <&gcc PCIE_2_AUX_CLK>,
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+ <&gcc PCIE_2_ALT_REF_CLK>;
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+ clock-names = "core", "iface", "phy", "aux", "ref";
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+
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+ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
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+ assigned-clock-rates = <100000000>;
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resets = <&gcc PCIE_2_ACLK_RESET>,
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<&gcc PCIE_2_HCLK_RESET>,
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<&gcc PCIE_2_POR_RESET>,
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<&gcc PCIE_2_PCI_RESET>,
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- <&gcc PCIE_2_PHY_RESET>;
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- reset-names = "axi", "ahb", "por", "pci", "phy";
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+ <&gcc PCIE_2_PHY_RESET>,
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+ <&gcc PCIE_2_EXT_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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status = "disabled";
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};
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