9b1b89229f
Removed upstreamed patches:
pending-5.4/499-mtd-parser-cmdline-Fix-parsing-of-part-names-with-co.patch
Manually merged:
pending-5.4/611-netfilter_match_bypass_default_table.patch
layerscape/302-dts-0112-arm64-dts-fsl-ls1028a-prepare-dts-for-overlay.patch
Build-tested: ipq806x/R7800, bcm27xx/bcm2711, ath79/{generic,tiny},
ipq40xx, octeon, ramips/mt7621, realtek, x86/64
Run-tested: ipq806x/R7800, realtek
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Tested-by: John Audia <graysky@archlinux.us>
Tested-by: Stijn Segers <foss@volatilesystems.org>
453 lines
9.8 KiB
Diff
453 lines
9.8 KiB
Diff
From a5009b362d65c24e7b2a40824e351903d75a47dc Mon Sep 17 00:00:00 2001
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From: Alex Marginean <alexandru.marginean@nxp.com>
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Date: Mon, 6 Jan 2020 16:36:44 +0200
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Subject: [PATCH] arm64: dts: fsl-ls1028a: prepare dts for overlay
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Named the ports node of the Felix Eth switch so it can be used in DT
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overlays to associate the ports with proper PHYs.
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Ports are now by default disabled in dtsi, so if the board dts doesn't
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do anything about them they stay disabled.
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Updated RDB and QDS dts files to match.
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Replaced all 'phy-connection-type' with 'phy-mode'.
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The set-up for protocol 7777 on QDS was changed to a single quad port card
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in slot 1. This requires a QDS board with no lane B rework and a AQR412
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or similar PHY card without any lane rework done on it.
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Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
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---
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.../boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi | 58 ++++++++++-----------
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.../boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi | 59 ++++++++++------------
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.../boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi | 51 ++++++++++++-------
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.../boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi | 43 ++++++++++------
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arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 44 +++++++++-------
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arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 27 +++++++---
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6 files changed, 161 insertions(+), 121 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtsi
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@@ -7,50 +7,50 @@
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*/
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&mdio_slot1 {
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- /* two ports on AQR412 */
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- slot1_sxgmii2: ethernet-phy@2 {
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- reg = <0x2>;
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+ slot1_sxgmii0: ethernet-phy@0 {
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+ reg = <0x0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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- slot1_sxgmii3: ethernet-phy@3 {
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- reg = <0x3>;
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+
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+ slot1_sxgmii1: ethernet-phy@1 {
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+ reg = <0x1>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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-};
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-&mdio_slot2 {
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- slot2_sxgmii0: ethernet-phy@2 {
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- /* AQR112 */
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+ slot1_sxgmii2: ethernet-phy@2 {
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reg = <0x2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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-};
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-&mdio_slot3 {
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- slot3_sxgmii0: ethernet-phy@2 {
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- /* AQR112 */
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- reg = <0x2>;
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+ slot1_sxgmii3: ethernet-phy@3 {
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+ reg = <0x3>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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/* l2switch ports */
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-&switch_port0 {
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- phy-handle = <&slot1_sxgmii2>;
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- phy-connection-type = "2500base-x";
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-};
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+&mscc_felix_ports {
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+ port@0 {
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+ status = "okay";
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+ phy-handle = <&slot1_sxgmii0>;
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+ phy-mode = "2500base-x";
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+ };
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-&switch_port1 {
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- phy-handle = <&slot2_sxgmii0>;
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- phy-connection-type = "2500base-x";
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-};
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+ port@1 {
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+ status = "okay";
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+ phy-handle = <&slot1_sxgmii1>;
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+ phy-mode = "2500base-x";
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+ };
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-&switch_port2 {
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- phy-handle = <&slot3_sxgmii0>;
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- phy-connection-type = "2500base-x";
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-};
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+ port@2 {
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+ status = "okay";
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+ phy-handle = <&slot1_sxgmii2>;
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+ phy-mode = "2500base-x";
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+ };
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-&switch_port3 {
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- phy-handle = <&slot1_sxgmii3>;
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- phy-connection-type = "2500base-x";
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+ port@3 {
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+ status = "okay";
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+ phy-handle = <&slot1_sxgmii3>;
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+ phy-mode = "2500base-x";
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+ };
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};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtsi
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@@ -11,50 +11,47 @@
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slot1_sgmii0: ethernet-phy@1c {
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reg = <0x1c>;
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};
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+
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slot1_sgmii1: ethernet-phy@1d {
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reg = <0x1d>;
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};
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+
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slot1_sgmii2: ethernet-phy@1e {
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reg = <0x1e>;
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};
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- slot1_sgmii3: ethernet-phy@1f {
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- reg = <0x1f>;
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- };
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-};
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-&mdio_slot2 {
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- /* VSC8234 */
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- slot2_sgmii0: ethernet-phy@1c {
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- reg = <0x1c>;
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- };
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- slot2_sgmii1: ethernet-phy@1d {
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- reg = <0x1d>;
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- };
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- slot2_sgmii2: ethernet-phy@1e {
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- reg = <0x1e>;
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- };
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- slot2_sgmii3: ethernet-phy@1f {
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+ slot1_sgmii3: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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/* l2switch ports */
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-&switch_port0 {
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- phy-handle = <&slot1_sgmii0>;
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- phy-connection-type = "sgmii";
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-};
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+&mscc_felix_ports {
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+ port@0 {
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+ status = "okay";
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+ phy-handle = <&slot1_sgmii0>;
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+ phy-mode = "sgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port1 {
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- phy-handle = <&slot2_sgmii0>;
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- phy-connection-type = "sgmii";
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-};
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+ port@1 {
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+ status = "okay";
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+ phy-handle = <&slot1_sgmii1>;
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+ phy-mode = "sgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port2 {
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- phy-handle = <&slot1_sgmii2>;
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- phy-connection-type = "sgmii";
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-};
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+ port@2 {
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+ status = "okay";
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+ phy-handle = <&slot1_sgmii2>;
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+ phy-mode = "sgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port3 {
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- phy-handle = <&slot1_sgmii3>;
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- phy-connection-type = "sgmii";
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+ port@3 {
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+ status = "okay";
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+ phy-handle = <&slot1_sgmii3>;
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+ phy-mode = "sgmii";
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+ managed = "in-band-status";
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+ };
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};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x3xx.dtsi
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@@ -8,41 +8,54 @@
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&mdio_slot2 {
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/* 4 ports on AQR412 */
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- slot2_qsgmii0: ethernet-phy@0 {
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+ slot2_qxgmii0: ethernet-phy@0 {
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reg = <0x0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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- slot2_qsgmii1: ethernet-phy@1 {
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+
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+ slot2_qxgmii1: ethernet-phy@1 {
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reg = <0x1>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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- slot2_qsgmii2: ethernet-phy@2 {
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+
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+ slot2_qxgmii2: ethernet-phy@2 {
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reg = <0x2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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- slot2_qsgmii3: ethernet-phy@3 {
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+
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+ slot2_qxgmii3: ethernet-phy@3 {
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reg = <0x3>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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/* l2switch ports */
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-&switch_port0 {
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- phy-handle = <&slot2_qsgmii0>;
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- phy-connection-type = "usxgmii";
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-};
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+&mscc_felix_ports {
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+ port@0 {
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+ status = "okay";
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+ phy-handle = <&slot2_qxgmii0>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port1 {
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- phy-handle = <&slot2_qsgmii1>;
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- phy-connection-type = "usxgmii";
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-};
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+ port@1 {
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+ status = "okay";
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+ phy-handle = <&slot2_qxgmii1>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port2 {
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- phy-handle = <&slot2_qsgmii2>;
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- phy-connection-type = "usxgmii";
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-};
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+ port@2 {
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+ status = "okay";
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+ phy-handle = <&slot2_qxgmii2>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port3 {
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- phy-handle = <&slot2_qsgmii3>;
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- phy-connection-type = "usxgmii";
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+ port@3 {
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+ status = "okay";
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+ phy-handle = <&slot2_qxgmii3>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ };
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};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-x5xx.dtsi
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@@ -11,34 +11,47 @@
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slot2_qsgmii0: ethernet-phy@8 {
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reg = <0x8>;
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};
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+
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slot2_qsgmii1: ethernet-phy@9 {
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reg = <0x9>;
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};
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+
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slot2_qsgmii2: ethernet-phy@a {
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reg = <0xa>;
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};
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+
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slot2_qsgmii3: ethernet-phy@b {
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reg = <0xb>;
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};
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};
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/* l2switch ports */
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-&switch_port0 {
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- phy-handle = <&slot2_qsgmii0>;
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- phy-connection-type = "qsgmii";
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-};
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+&mscc_felix_ports {
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+ port@0 {
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+ status = "okay";
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+ phy-handle = <&slot2_qsgmii0>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port1 {
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- phy-handle = <&slot2_qsgmii1>;
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- phy-connection-type = "qsgmii";
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-};
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+ port@1 {
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+ status = "okay";
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+ phy-handle = <&slot2_qsgmii1>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port2 {
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- phy-handle = <&slot2_qsgmii2>;
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- phy-connection-type = "qsgmii";
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-};
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+ port@2 {
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+ status = "okay";
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+ phy-handle = <&slot2_qsgmii2>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port3 {
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- phy-handle = <&slot2_qsgmii3>;
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- phy-connection-type = "qsgmii";
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+ port@3 {
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+ status = "okay";
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+ phy-handle = <&slot2_qsgmii3>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ };
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};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
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@@ -233,28 +233,34 @@
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};
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/* l2switch ports */
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-&switch_port0 {
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- phy-handle = <&qsgmii_phy1>;
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- phy-connection-type = "qsgmii";
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- managed = "in-band-status";
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-};
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+&mscc_felix_ports {
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+ port@0 {
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+ status = "okay";
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+ phy-handle = <&qsgmii_phy1>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port1 {
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- phy-handle = <&qsgmii_phy2>;
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- phy-connection-type = "qsgmii";
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- managed = "in-band-status";
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-};
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+ port@1 {
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+ status = "okay";
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+ phy-handle = <&qsgmii_phy2>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port2 {
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- phy-handle = <&qsgmii_phy3>;
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- phy-connection-type = "qsgmii";
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- managed = "in-band-status";
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-};
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+ port@2 {
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+ status = "okay";
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+ phy-handle = <&qsgmii_phy3>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ };
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-&switch_port3 {
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- phy-handle = <&qsgmii_phy4>;
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- phy-connection-type = "qsgmii";
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- managed = "in-band-status";
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+ port@3 {
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+ status = "okay";
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+ phy-handle = <&qsgmii_phy4>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ };
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};
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&sai4 {
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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@@ -774,30 +774,39 @@
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clocks = <&clockgen 2 3>;
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little-endian;
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};
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- switch@0,5 {
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+
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+ ethernet-switch@0,5 {
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reg = <0x000500 0 0 0 0>;
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/* IEP INT_B */
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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- ports {
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+ mscc_felix_ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* external ports */
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- switch_port0: port@0 {
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+ mscc_felix_port0: port@0 {
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reg = <0>;
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+ status = "disabled";
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};
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- switch_port1: port@1 {
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+
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+ mscc_felix_port1: port@1 {
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reg = <1>;
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+ status = "disabled";
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};
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- switch_port2: port@2 {
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+
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+ mscc_felix_port2: port@2 {
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reg = <2>;
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+ status = "disabled";
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};
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- switch_port3: port@3 {
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+
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+ mscc_felix_port3: port@3 {
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reg = <3>;
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+ status = "disabled";
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};
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+
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/* internal to-cpu ports */
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- port@4 {
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+ mscc_felix_port4: port@4 {
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reg = <4>;
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ethernet = <&enetc_port2>;
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phy-mode = "gmii";
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@@ -807,7 +816,8 @@
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full-duplex;
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};
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};
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- port@5 {
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+
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+ mscc_felix_port5: port@5 {
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reg = <5>;
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phy-mode = "gmii";
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status = "disabled";
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@@ -819,6 +829,7 @@
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};
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};
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};
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+
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enetc_port3: ethernet@0,6 {
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compatible = "fsl,enetc";
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reg = <0x000600 0 0 0 0>;
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