08d8a3646b
These patches have been accepted for linux v5.13. External interrupts not supported for now. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
218 lines
6.0 KiB
Diff
218 lines
6.0 KiB
Diff
From ff8324355d7ae2e4ebbd304de27bb5fa75e20c6a Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
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Date: Wed, 24 Mar 2021 09:19:19 +0100
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Subject: [PATCH 18/22] dt-bindings: add BCM63268 GPIO sysctl binding
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documentation
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add binding documentation for the GPIO sysctl found in BCM63268 SoCs.
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Link: https://lore.kernel.org/r/20210324081923.20379-19-noltari@gmail.com
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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.../mfd/brcm,bcm63268-gpio-sysctl.yaml | 194 ++++++++++++++++++
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1 file changed, 194 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml
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@@ -0,0 +1,194 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings
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+
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+maintainers:
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+ - Álvaro Fernández Rojas <noltari@gmail.com>
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+ - Jonas Gorski <jonas.gorski@gmail.com>
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+
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+description:
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+ Broadcom BCM63268 SoC GPIO system controller which provides a register map
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+ for controlling the GPIO and pins of the SoC.
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+
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+properties:
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+ "#address-cells": true
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+
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+ "#size-cells": true
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+
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+ compatible:
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+ items:
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+ - const: brcm,bcm63268-gpio-sysctl
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+ - const: syscon
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+ - const: simple-mfd
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+
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+ ranges:
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+ maxItems: 1
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+
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+ reg:
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+ maxItems: 1
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+
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+patternProperties:
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+ "^gpio@[0-9a-f]+$":
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+ # Child node
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+ type: object
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+ $ref: "../gpio/brcm,bcm6345-gpio.yaml"
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+ description:
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+ GPIO controller for the SoC GPIOs. This child node definition
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+ should follow the bindings specified in
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+ Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
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+
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+ "^pinctrl@[0-9a-f]+$":
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+ # Child node
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+ type: object
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+ $ref: "../pinctrl/brcm,bcm63268-pinctrl.yaml"
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+ description:
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+ Pin controller for the SoC pins. This child node definition
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+ should follow the bindings specified in
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+ Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml.
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+
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+required:
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+ - "#address-cells"
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+ - compatible
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+ - ranges
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+ - reg
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+ - "#size-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ syscon@100000c0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "brcm,bcm63268-gpio-sysctl", "syscon", "simple-mfd";
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+ reg = <0x100000c0 0x80>;
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+ ranges = <0 0x100000c0 0x80>;
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+
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+ gpio@0 {
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+ compatible = "brcm,bcm63268-gpio";
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+ reg-names = "dirout", "dat";
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+ reg = <0x0 0x8>, <0x8 0x8>;
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+
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+ gpio-controller;
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+ gpio-ranges = <&pinctrl 0 0 52>;
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+ #gpio-cells = <2>;
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+ };
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+
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+ pinctrl: pinctrl@10 {
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+ compatible = "brcm,bcm63268-pinctrl";
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+ reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
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+
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+ pinctrl_serial_led: serial_led-pins {
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+ pinctrl_serial_led_clk: serial_led_clk-pins {
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+ function = "serial_led_clk";
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+ pins = "gpio0";
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+ };
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+
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+ pinctrl_serial_led_data: serial_led_data-pins {
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+ function = "serial_led_data";
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+ pins = "gpio1";
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+ };
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+ };
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+
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+ pinctrl_hsspi_cs4: hsspi_cs4-pins {
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+ function = "hsspi_cs4";
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+ pins = "gpio16";
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+ };
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+
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+ pinctrl_hsspi_cs5: hsspi_cs5-pins {
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+ function = "hsspi_cs5";
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+ pins = "gpio17";
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+ };
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+
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+ pinctrl_hsspi_cs6: hsspi_cs6-pins {
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+ function = "hsspi_cs6";
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+ pins = "gpio8";
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+ };
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+
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+ pinctrl_hsspi_cs7: hsspi_cs7-pins {
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+ function = "hsspi_cs7";
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+ pins = "gpio9";
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+ };
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+
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+ pinctrl_adsl_spi: adsl_spi-pins {
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+ pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
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+ function = "adsl_spi_miso";
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+ pins = "gpio18";
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+ };
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+
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+ pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
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+ function = "adsl_spi_mosi";
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+ pins = "gpio19";
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+ };
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+ };
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+
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+ pinctrl_vreq_clk: vreq_clk-pins {
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+ function = "vreq_clk";
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+ pins = "gpio22";
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+ };
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+
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+ pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
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+ function = "pcie_clkreq_b";
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+ pins = "gpio23";
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+ };
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+
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+ pinctrl_robosw_led_clk: robosw_led_clk-pins {
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+ function = "robosw_led_clk";
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+ pins = "gpio30";
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+ };
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+
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+ pinctrl_robosw_led_data: robosw_led_data-pins {
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+ function = "robosw_led_data";
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+ pins = "gpio31";
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+ };
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+
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+ pinctrl_nand: nand-pins {
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+ function = "nand";
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+ group = "nand_grp";
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+ };
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+
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+ pinctrl_gpio35_alt: gpio35_alt-pins {
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+ function = "gpio35_alt";
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+ pin = "gpio35";
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+ };
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+
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+ pinctrl_dectpd: dectpd-pins {
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+ function = "dectpd";
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+ group = "dectpd_grp";
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+ };
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+
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+ pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
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+ function = "vdsl_phy_override_0";
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+ group = "vdsl_phy_override_0_grp";
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+ };
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+
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+ pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
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+ function = "vdsl_phy_override_1";
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+ group = "vdsl_phy_override_1_grp";
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+ };
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+
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+ pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
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+ function = "vdsl_phy_override_2";
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+ group = "vdsl_phy_override_2_grp";
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+ };
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+
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+ pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
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+ function = "vdsl_phy_override_3";
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+ group = "vdsl_phy_override_3_grp";
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+ };
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+
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+ pinctrl_dsl_gpio8: dsl_gpio8-pins {
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+ function = "dsl_gpio8";
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+ group = "dsl_gpio8";
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+ };
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+
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+ pinctrl_dsl_gpio9: dsl_gpio9-pins {
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+ function = "dsl_gpio9";
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+ group = "dsl_gpio9";
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+ };
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+ };
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+ };
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