134 lines
3.9 KiB
Diff
134 lines
3.9 KiB
Diff
From 3f4570c9794fcae1cf62fbf3266a2e23edac67a5 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Wed, 27 Jun 2012 15:01:09 +0200
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Subject: [PATCH 3/7] MIPS: BCM63XX: rework chip detection
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Instead of trying to use a correlation of cpu prid and chip id and
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hoping they will always be unique, use the cpu prid to determine the
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chip id register location and just read out the chip id.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/cpu.c | 87 +++++++++++++++++++++++------------------------
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1 file changed, 42 insertions(+), 45 deletions(-)
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--- a/arch/mips/bcm63xx/cpu.c
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+++ b/arch/mips/bcm63xx/cpu.c
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@@ -240,53 +240,27 @@ static unsigned int detect_memory_size(v
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void __init bcm63xx_cpu_init(void)
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{
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- unsigned int tmp, expected_cpu_id;
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+ unsigned int tmp;
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int cpu = smp_processor_id();
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+ u32 chipid_reg;
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/* soc registers location depends on cpu type */
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- expected_cpu_id = 0;
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+ chipid_reg = 0;
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switch (c->cputype) {
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case CPU_BMIPS3300:
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- if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
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- expected_cpu_id = BCM6348_CPU_ID;
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- bcm63xx_regs_base = bcm6348_regs_base;
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- bcm63xx_irqs = bcm6348_irqs;
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- } else {
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+ if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT)
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__cpu_name[cpu] = "Broadcom BCM6338";
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- expected_cpu_id = BCM6338_CPU_ID;
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- bcm63xx_regs_base = bcm6338_regs_base;
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- bcm63xx_irqs = bcm6338_irqs;
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- }
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- break;
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+ /* fall-through */
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case CPU_BMIPS32:
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- expected_cpu_id = BCM6345_CPU_ID;
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- bcm63xx_regs_base = bcm6345_regs_base;
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- bcm63xx_irqs = bcm6345_irqs;
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+ chipid_reg = BCM_6345_PERF_BASE;
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break;
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case CPU_BMIPS4350:
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- if ((read_c0_prid() & 0xf0) == 0x10) {
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- expected_cpu_id = BCM6358_CPU_ID;
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- bcm63xx_regs_base = bcm6358_regs_base;
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- bcm63xx_irqs = bcm6358_irqs;
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- } else {
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- /* all newer chips have the same chip id location */
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- u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
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-
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- switch (chip_id) {
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- case BCM6328_CPU_ID:
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- expected_cpu_id = BCM6328_CPU_ID;
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- bcm63xx_regs_base = bcm6328_regs_base;
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- bcm63xx_irqs = bcm6328_irqs;
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- break;
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- case BCM6368_CPU_ID:
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- expected_cpu_id = BCM6368_CPU_ID;
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- bcm63xx_regs_base = bcm6368_regs_base;
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- bcm63xx_irqs = bcm6368_irqs;
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- break;
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- }
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- }
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+ if ((read_c0_prid() & 0xf0) == 0x10)
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+ chipid_reg = BCM_6345_PERF_BASE;
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+ else
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+ chipid_reg = BCM_6368_PERF_BASE;
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break;
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}
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@@ -294,20 +268,43 @@ void __init bcm63xx_cpu_init(void)
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* really early to panic, but delaying panic would not help since we
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* will never get any working console
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*/
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- if (!expected_cpu_id)
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+ if (!chipid_reg)
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panic("unsupported Broadcom CPU");
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- /*
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- * bcm63xx_regs_base is set, we can access soc registers
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- */
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-
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- /* double check CPU type */
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- tmp = bcm_perf_readl(PERF_REV_REG);
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+ /* read out CPU type */
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+ tmp = bcm_readl(chipid_reg);
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bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
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bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
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- if (bcm63xx_cpu_id != expected_cpu_id)
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- panic("bcm63xx CPU id mismatch");
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+ switch (bcm63xx_cpu_id) {
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+ case BCM6328_CPU_ID:
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+ bcm63xx_regs_base = bcm6328_regs_base;
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+ bcm63xx_irqs = bcm6328_irqs;
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+ break;
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+ case BCM6338_CPU_ID:
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+ bcm63xx_regs_base = bcm6338_regs_base;
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+ bcm63xx_irqs = bcm6338_irqs;
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+ break;
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+ case BCM6345_CPU_ID:
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+ bcm63xx_regs_base = bcm6345_regs_base;
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+ bcm63xx_irqs = bcm6345_irqs;
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+ break;
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+ case BCM6348_CPU_ID:
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+ bcm63xx_regs_base = bcm6348_regs_base;
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+ bcm63xx_irqs = bcm6348_irqs;
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+ break;
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+ case BCM6358_CPU_ID:
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+ bcm63xx_regs_base = bcm6358_regs_base;
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+ bcm63xx_irqs = bcm6358_irqs;
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+ break;
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+ case BCM6368_CPU_ID:
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+ bcm63xx_regs_base = bcm6368_regs_base;
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+ bcm63xx_irqs = bcm6368_irqs;
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+ break;
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+ default:
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+ panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
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+ break;
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+ }
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bcm63xx_cpu_freq = detect_cpu_clock();
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bcm63xx_memory_size = detect_memory_size();
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