706 lines
22 KiB
Diff
706 lines
22 KiB
Diff
From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
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Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
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From: Matthias Schiffer <mschiffer@universe-factory.net>
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Date: Sat, 29 Mar 2014 20:26:08 +0100
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Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
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Note that the clock calculation looks very similar to the QCA955x, but the
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meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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---
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arch/mips/ath79/Kconfig | 6 +-
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arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++
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arch/mips/ath79/common.c | 4 ++
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arch/mips/ath79/dev-common.c | 1 +
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arch/mips/ath79/dev-wmac.c | 20 +++++++
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arch/mips/ath79/early_printk.c | 1 +
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arch/mips/ath79/gpio.c | 4 +-
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arch/mips/ath79/irq.c | 4 ++
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arch/mips/ath79/setup.c | 8 ++-
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
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arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
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11 files changed, 182 insertions(+), 3 deletions(-)
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -117,6 +117,10 @@ config SOC_AR934X
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select PCI_AR724X if PCI
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def_bool n
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+config SOC_QCA953X
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+ select USB_ARCH_HAS_EHCI
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+ def_bool n
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+
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config SOC_QCA955X
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select HW_HAS_PCI
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select PCI_AR724X if PCI
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@@ -156,7 +160,7 @@ config ATH79_DEV_USB
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def_bool n
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config ATH79_DEV_WMAC
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- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
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+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
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def_bool n
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config ATH79_NVRAM
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -354,6 +354,91 @@ static void __init ar934x_clocks_init(vo
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iounmap(dpll_base);
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}
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+static void __init qca953x_clocks_init(void)
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+{
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+ unsigned long ref_rate;
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+ unsigned long cpu_rate;
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+ unsigned long ddr_rate;
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+ unsigned long ahb_rate;
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+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
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+ ref_rate = 40 * 1000 * 1000;
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+ else
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+ ref_rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
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+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
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+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
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+
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+ cpu_pll = nint * ref_rate / ref_div;
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+ cpu_pll += frac * (ref_rate >> 6) / ref_div;
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+ cpu_pll /= (1 << out_div);
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
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+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
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+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
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+
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+ ddr_pll = nint * ref_rate / ref_div;
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+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
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+ ddr_pll /= (1 << out_div);
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+
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+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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+ cpu_rate = ref_rate;
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+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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+ cpu_rate = cpu_pll / (postdiv + 1);
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+ else
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+ cpu_rate = ddr_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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+ ddr_rate = ref_rate;
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+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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+ ddr_rate = ddr_pll / (postdiv + 1);
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+ else
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+ ddr_rate = cpu_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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+ ahb_rate = ref_rate;
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+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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+ ahb_rate = ddr_pll / (postdiv + 1);
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+ else
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+ ahb_rate = cpu_pll / (postdiv + 1);
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+
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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+
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+ clk_add_alias("wdt", NULL, "ref", NULL);
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+ clk_add_alias("uart", NULL, "ref", NULL);
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+}
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+
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static void __init qca955x_clocks_init(void)
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{
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unsigned long ref_rate;
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@@ -451,6 +536,8 @@ void __init ath79_clocks_init(void)
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ar933x_clocks_init();
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else if (soc_is_ar934x())
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ar934x_clocks_init();
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+ else if (soc_is_qca953x())
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+ qca953x_clocks_init();
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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else
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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -104,6 +104,8 @@ void ath79_device_reset_set(u32 mask)
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca953x())
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+ reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else
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@@ -132,6 +134,8 @@ void ath79_device_reset_clear(u32 mask)
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca953x())
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+ reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else
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--- a/arch/mips/ath79/dev-common.c
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+++ b/arch/mips/ath79/dev-common.c
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@@ -94,6 +94,7 @@ void __init ath79_register_uart(void)
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soc_is_ar724x() ||
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soc_is_ar913x() ||
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soc_is_ar934x() ||
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+ soc_is_qca953x() ||
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soc_is_qca955x()) {
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ath79_uart_data[0].uartclk = uart_clk_rate;
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platform_device_register(&ath79_uart_device);
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@@ -157,6 +158,9 @@ void __init ath79_gpio_init(void)
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} else if (soc_is_ar934x()) {
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ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
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ath79_gpio_pdata.oe_inverted = 1;
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+ } else if (soc_is_qca953x()) {
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+ ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT;
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+ ath79_gpio_pdata.oe_inverted = 1;
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} else if (soc_is_qca955x()) {
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ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
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ath79_gpio_pdata.oe_inverted = 1;
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--- a/arch/mips/ath79/dev-usb.c
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+++ b/arch/mips/ath79/dev-usb.c
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@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
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&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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}
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+static void __init qca953x_usb_setup(void)
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+{
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+
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+ ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
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+ udelay(1000);
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+
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+ ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
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+ udelay(1000);
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+
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+ ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
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+ udelay(1000);
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+
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+ ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
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+ udelay(1000);
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+
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+ ath79_usb_register("ehci-platform", -1,
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+ QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE,
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+ ATH79_CPU_IRQ(3),
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+ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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+}
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+
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static void qca955x_usb_reset_notifier(struct platform_device *pdev)
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{
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u32 base;
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@@ -286,6 +310,8 @@ void __init ath79_register_usb(void)
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ar933x_usb_setup();
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else if (soc_is_ar934x())
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ar934x_usb_setup();
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+ else if (soc_is_qca953x())
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+ qca953x_usb_setup();
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else if (soc_is_qca955x())
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qca955x_usb_setup();
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else
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
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return -ETIMEDOUT;
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}
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-static int ar933x_r1_get_wmac_revision(void)
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+static int ar93xx_get_soc_revision(void)
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{
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return ath79_soc_rev;
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}
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@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
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ath79_wmac_data.is_clk_25mhz = true;
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if (ath79_soc_rev == 1)
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- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
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+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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ath79_wmac_data.external_reset = ar933x_wmac_reset;
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}
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@@ -151,6 +151,26 @@ static void ar934x_wmac_setup(void)
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ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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}
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+static void qca953x_wmac_setup(void)
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+{
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+ u32 t;
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+
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+ ath79_wmac_device.name = "qca953x_wmac";
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+
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+ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
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+ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
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+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
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+ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
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+
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+ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
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+ ath79_wmac_data.is_clk_25mhz = false;
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+ else
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+ ath79_wmac_data.is_clk_25mhz = true;
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+
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+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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+}
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+
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static void qca955x_wmac_setup(void)
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{
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u32 t;
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@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_
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ar933x_wmac_setup();
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else if (soc_is_ar934x())
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ar934x_wmac_setup();
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+ else if (soc_is_qca953x())
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+ qca953x_wmac_setup();
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else if (soc_is_qca955x())
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qca955x_wmac_setup();
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else
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--- a/arch/mips/ath79/early_printk.c
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+++ b/arch/mips/ath79/early_printk.c
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@@ -116,6 +116,8 @@ static void prom_putchar_init(void)
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case REV_ID_MAJOR_AR9341:
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case REV_ID_MAJOR_AR9342:
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case REV_ID_MAJOR_AR9344:
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+ case REV_ID_MAJOR_QCA9533:
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+ case REV_ID_MAJOR_QCA9533_V2:
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case REV_ID_MAJOR_QCA9556:
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case REV_ID_MAJOR_QCA9558:
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_prom_putchar = prom_putchar_ar71xx;
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--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -31,7 +31,7 @@ static void __iomem *ath79_gpio_get_func
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soc_is_ar913x() ||
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soc_is_ar933x())
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reg = AR71XX_GPIO_REG_FUNC;
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- else if (soc_is_ar934x())
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+ else if (soc_is_ar934x() || soc_is_qca953x())
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reg = AR934X_GPIO_REG_FUNC;
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else
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BUG();
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@@ -64,7 +64,7 @@ void __init ath79_gpio_output_select(uns
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unsigned int reg;
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u32 t, s;
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- BUG_ON(!soc_is_ar934x());
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+ BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
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if (gpio >= AR934X_GPIO_COUNT)
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return;
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--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -105,6 +105,7 @@ static void __init ath79_misc_irq_init(v
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else if (soc_is_ar724x() ||
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soc_is_ar933x() ||
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soc_is_ar934x() ||
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+ soc_is_qca953x() ||
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soc_is_qca955x())
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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else
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@@ -148,6 +149,34 @@ static void ar934x_ip2_irq_init(void)
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irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
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}
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+static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
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+{
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+ u32 status;
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+
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+ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
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+
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+ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
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+ ath79_ddr_wb_flush(3);
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+ generic_handle_irq(ATH79_IP2_IRQ(0));
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+ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
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+ ath79_ddr_wb_flush(4);
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+ generic_handle_irq(ATH79_IP2_IRQ(1));
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+ } else {
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+ spurious_interrupt();
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+ }
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+}
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+
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+static void qca953x_irq_init(void)
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+{
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+ int i;
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+
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+ for (i = ATH79_IP2_IRQ_BASE;
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+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+
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+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
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+}
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+
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static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
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{
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u32 status;
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@@ -362,7 +391,7 @@ void __init arch_init_irq(void)
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soc_is_ar913x() || soc_is_ar933x()) {
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irq_wb_chan[2] = 3;
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irq_wb_chan[3] = 2;
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- } else if (soc_is_ar934x()) {
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+ } else if (soc_is_ar934x() || soc_is_qca953x()) {
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irq_wb_chan[3] = 2;
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}
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@@ -371,6 +400,8 @@ void __init arch_init_irq(void)
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if (soc_is_ar934x())
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ar934x_ip2_irq_init();
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+ else if (soc_is_qca953x())
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+ qca953x_irq_init();
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else if (soc_is_qca955x())
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qca955x_irq_init();
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}
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--- a/arch/mips/ath79/setup.c
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+++ b/arch/mips/ath79/setup.c
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@@ -64,6 +64,7 @@ static void __init ath79_detect_sys_type
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u32 major;
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u32 minor;
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u32 rev = 0;
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+ u32 ver = 1;
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id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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@@ -156,6 +157,17 @@ static void __init ath79_detect_sys_type
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
|
|
|
|
+ case REV_ID_MAJOR_QCA9533_V2:
|
|
+ ver = 2;
|
|
+ ath79_soc_rev = 2;
|
|
+ /* drop through */
|
|
+
|
|
+ case REV_ID_MAJOR_QCA9533:
|
|
+ ath79_soc = ATH79_SOC_QCA9533;
|
|
+ chip = "9533";
|
|
+ rev = id & QCA953X_REV_ID_REVISION_MASK;
|
|
+ break;
|
|
+
|
|
case REV_ID_MAJOR_QCA9556:
|
|
ath79_soc = ATH79_SOC_QCA9556;
|
|
chip = "9556";
|
|
@@ -172,11 +184,12 @@ static void __init ath79_detect_sys_type
|
|
panic("ath79: unknown SoC, id:0x%08x", id);
|
|
}
|
|
|
|
- ath79_soc_rev = rev;
|
|
+ if (ver == 1)
|
|
+ ath79_soc_rev = rev;
|
|
|
|
- if (soc_is_qca955x())
|
|
- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
|
|
- chip, rev);
|
|
+ if (soc_is_qca953x() || soc_is_qca955x())
|
|
+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
|
|
+ chip, ver, rev);
|
|
else
|
|
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
|
|
pr_info("SoC: %s\n", ath79_sys_type);
|
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
@@ -105,6 +105,21 @@
|
|
#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
|
|
#define AR934X_SRIF_SIZE 0x1000
|
|
|
|
+#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
|
|
+#define QCA953X_GMAC_SIZE 0x14
|
|
+#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
|
+#define QCA953X_WMAC_SIZE 0x20000
|
|
+#define QCA953X_EHCI_BASE 0x1b000000
|
|
+#define QCA953X_EHCI_SIZE 0x200
|
|
+#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
|
|
+#define QCA953X_SRIF_SIZE 0x1000
|
|
+
|
|
+#define QCA953X_PCI_CFG_BASE0 0x14000000
|
|
+#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
|
|
+#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
|
|
+#define QCA953X_PCI_MEM_BASE0 0x10000000
|
|
+#define QCA953X_PCI_MEM_SIZE 0x02000000
|
|
+
|
|
#define QCA955X_PCI_MEM_BASE0 0x10000000
|
|
#define QCA955X_PCI_MEM_BASE1 0x12000000
|
|
#define QCA955X_PCI_MEM_SIZE 0x02000000
|
|
@@ -173,6 +188,12 @@
|
|
#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
|
|
#define AR934X_DDR_REG_FLUSH_WMAC 0xac
|
|
|
|
+#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
|
|
+#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
|
|
+#define QCA953X_DDR_REG_FLUSH_USB 0xa4
|
|
+#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
|
|
+#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
|
|
+
|
|
/*
|
|
* PLL block
|
|
*/
|
|
@@ -279,6 +300,44 @@
|
|
|
|
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
|
|
|
|
+#define QCA953X_PLL_CPU_CONFIG_REG 0x00
|
|
+#define QCA953X_PLL_DDR_CONFIG_REG 0x04
|
|
+#define QCA953X_PLL_CLK_CTRL_REG 0x08
|
|
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
|
|
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
|
|
+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
|
|
+
|
|
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
|
|
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
|
|
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
|
|
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
|
|
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
|
|
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
|
|
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
|
|
+
|
|
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
|
|
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
|
|
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
|
|
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
|
|
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
|
|
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
|
|
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
|
|
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
|
|
+
|
|
+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
|
|
+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
|
|
+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
|
|
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
|
|
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
|
|
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
|
|
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
|
|
+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
|
|
+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
|
|
+
|
|
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
|
|
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
|
|
#define QCA955X_PLL_CLK_CTRL_REG 0x08
|
|
@@ -355,6 +414,10 @@
|
|
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
|
|
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
|
|
|
+#define QCA953X_RESET_REG_RESET_MODULE 0x1c
|
|
+#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
|
|
+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
|
+
|
|
#define QCA955X_RESET_REG_RESET_MODULE 0x1c
|
|
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
|
|
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
|
|
@@ -450,6 +513,27 @@
|
|
#define AR934X_RESET_MBOX BIT(1)
|
|
#define AR934X_RESET_I2S BIT(0)
|
|
|
|
+#define QCA953X_RESET_USB_EXT_PWR BIT(29)
|
|
+#define QCA953X_RESET_EXTERNAL BIT(28)
|
|
+#define QCA953X_RESET_RTC BIT(27)
|
|
+#define QCA953X_RESET_FULL_CHIP BIT(24)
|
|
+#define QCA953X_RESET_GE1_MDIO BIT(23)
|
|
+#define QCA953X_RESET_GE0_MDIO BIT(22)
|
|
+#define QCA953X_RESET_CPU_NMI BIT(21)
|
|
+#define QCA953X_RESET_CPU_COLD BIT(20)
|
|
+#define QCA953X_RESET_DDR BIT(16)
|
|
+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
|
|
+#define QCA953X_RESET_GE1_MAC BIT(13)
|
|
+#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
|
|
+#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
|
|
+#define QCA953X_RESET_GE0_MAC BIT(9)
|
|
+#define QCA953X_RESET_ETH_SWITCH BIT(8)
|
|
+#define QCA953X_RESET_PCIE_PHY BIT(7)
|
|
+#define QCA953X_RESET_PCIE BIT(6)
|
|
+#define QCA953X_RESET_USB_HOST BIT(5)
|
|
+#define QCA953X_RESET_USB_PHY BIT(4)
|
|
+#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
|
|
+
|
|
#define QCA955X_RESET_HOST BIT(31)
|
|
#define QCA955X_RESET_SLIC BIT(30)
|
|
#define QCA955X_RESET_HDMA BIT(29)
|
|
@@ -503,6 +587,13 @@
|
|
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
|
#define AR934X_BOOTSTRAP_DDR1 BIT(0)
|
|
|
|
+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
|
|
+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
|
|
+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
|
|
+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
|
+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
|
+#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
|
|
+
|
|
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
|
|
|
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
|
@@ -523,6 +614,24 @@
|
|
AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
|
|
AR934X_PCIE_WMAC_INT_PCIE_RC3)
|
|
|
|
+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
|
+#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
|
|
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
|
|
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
|
|
+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
|
|
+ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
|
|
+ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
|
|
+
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
|
|
+ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
|
|
+ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
|
|
+ QCA953X_PCIE_WMAC_INT_PCIE_RC3)
|
|
+
|
|
#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
|
|
#define QCA955X_EXT_INT_WMAC_TX BIT(1)
|
|
#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
|
|
@@ -565,6 +674,8 @@
|
|
#define REV_ID_MAJOR_AR9341 0x0120
|
|
#define REV_ID_MAJOR_AR9342 0x1120
|
|
#define REV_ID_MAJOR_AR9344 0x2120
|
|
+#define REV_ID_MAJOR_QCA9533 0x0140
|
|
+#define REV_ID_MAJOR_QCA9533_V2 0x0160
|
|
#define REV_ID_MAJOR_QCA9556 0x0130
|
|
#define REV_ID_MAJOR_QCA9558 0x1130
|
|
|
|
@@ -587,6 +698,8 @@
|
|
|
|
#define AR934X_REV_ID_REVISION_MASK 0xf
|
|
|
|
+#define QCA953X_REV_ID_REVISION_MASK 0xf
|
|
+
|
|
#define QCA955X_REV_ID_REVISION_MASK 0xf
|
|
|
|
/*
|
|
@@ -634,6 +747,25 @@
|
|
#define AR934X_GPIO_REG_OUT_FUNC5 0x40
|
|
#define AR934X_GPIO_REG_FUNC 0x6c
|
|
|
|
+#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
|
|
+#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
|
|
+#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
|
|
+#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
|
|
+#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
|
|
+#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
|
|
+#define QCA953X_GPIO_REG_FUNC 0x6c
|
|
+
|
|
+#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
|
|
+#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
|
|
+#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
|
|
+#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
|
|
+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
|
|
+#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
|
|
+#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
|
|
+#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
|
|
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
|
|
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
|
|
+
|
|
#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
|
|
#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
|
|
#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
|
|
@@ -648,6 +780,7 @@
|
|
#define AR913X_GPIO_COUNT 22
|
|
#define AR933X_GPIO_COUNT 30
|
|
#define AR934X_GPIO_COUNT 23
|
|
+#define QCA953X_GPIO_COUNT 18
|
|
#define QCA955X_GPIO_COUNT 24
|
|
|
|
/*
|
|
@@ -671,6 +804,24 @@
|
|
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
|
|
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
|
|
|
|
+#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
|
|
+#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
|
|
+#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
|
|
+
|
|
+#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
|
|
+#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
|
|
+#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
|
|
+
|
|
+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
|
|
+#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
|
|
+#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
|
|
+#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
|
|
+#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
|
|
+
|
|
+#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
|
|
+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
|
|
+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
|
|
+
|
|
#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
|
|
#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
|
|
#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
|
|
@@ -877,6 +1028,16 @@
|
|
#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
|
|
|
|
/*
|
|
+ * QCA953X GMAC Interface
|
|
+ */
|
|
+#define QCA953X_GMAC_REG_ETH_CFG 0x00
|
|
+
|
|
+#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
|
|
+#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
|
|
+#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
|
|
+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
|
|
+
|
|
+/*
|
|
* QCA955X GMAC Interface
|
|
*/
|
|
|
|
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
|
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
|
@@ -32,6 +32,7 @@ enum ath79_soc_type {
|
|
ATH79_SOC_AR9341,
|
|
ATH79_SOC_AR9342,
|
|
ATH79_SOC_AR9344,
|
|
+ ATH79_SOC_QCA9533,
|
|
ATH79_SOC_QCA9556,
|
|
ATH79_SOC_QCA9558,
|
|
};
|
|
@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
|
|
return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
|
|
}
|
|
|
|
+static inline int soc_is_qca9533(void)
|
|
+{
|
|
+ return ath79_soc == ATH79_SOC_QCA9533;
|
|
+}
|
|
+
|
|
+static inline int soc_is_qca953x(void)
|
|
+{
|
|
+ return soc_is_qca9533();
|
|
+}
|
|
+
|
|
static inline int soc_is_qca9556(void)
|
|
{
|
|
return ath79_soc == ATH79_SOC_QCA9556;
|