680f91d0e5
Backport upstream patch that fixes TRGMII mode now that mt7530 is
actually resetting the switch on ramips devices.
Patches apply to both Linux 5.4 and 5.10, since TRGMII is broken on both.
Fixes: 69551a2442 ("ramips: manage low reset lines")
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
85 lines
2.7 KiB
Diff
85 lines
2.7 KiB
Diff
From c3b8e07909dbe67b0d580416c1a5257643a73be7 Mon Sep 17 00:00:00 2001
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From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
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Date: Fri, 12 Mar 2021 00:07:03 -0800
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Subject: [PATCH] net: dsa: mt7530: setup core clock even in TRGMII mode
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A recent change to MIPS ralink reset logic made it so mt7530 actually
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resets the switch on platforms such as mt7621 (where bit 2 is the reset
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line for the switch). That exposed an issue where the switch would not
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function properly in TRGMII mode after a reset.
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Reconfigure core clock in TRGMII mode to fix the issue.
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Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.
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Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
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Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++---------------------
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1 file changed, 25 insertions(+), 27 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -427,34 +427,32 @@ mt7530_pad_clk_setup(struct dsa_switch *
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TD_DM_DRVP(8) | TD_DM_DRVN(8));
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/* Setup core clock for MT7530 */
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- if (!trgint) {
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- /* Disable MT7530 core clock */
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- core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
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-
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- /* Disable PLL, since phy_device has not yet been created
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- * provided for phy_[read,write]_mmd_indirect is called, we
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- * provide our own core_write_mmd_indirect to complete this
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- * function.
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- */
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- core_write_mmd_indirect(priv,
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- CORE_GSWPLL_GRP1,
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- MDIO_MMD_VEND2,
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- 0);
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-
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- /* Set core clock into 500Mhz */
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- core_write(priv, CORE_GSWPLL_GRP2,
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- RG_GSWPLL_POSDIV_500M(1) |
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- RG_GSWPLL_FBKDIV_500M(25));
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-
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- /* Enable PLL */
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- core_write(priv, CORE_GSWPLL_GRP1,
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- RG_GSWPLL_EN_PRE |
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- RG_GSWPLL_POSDIV_200M(2) |
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- RG_GSWPLL_FBKDIV_200M(32));
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-
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- /* Enable MT7530 core clock */
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- core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
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- }
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+ /* Disable MT7530 core clock */
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+ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
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+
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+ /* Disable PLL, since phy_device has not yet been created
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+ * provided for phy_[read,write]_mmd_indirect is called, we
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+ * provide our own core_write_mmd_indirect to complete this
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+ * function.
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+ */
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+ core_write_mmd_indirect(priv,
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+ CORE_GSWPLL_GRP1,
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+ MDIO_MMD_VEND2,
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+ 0);
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+
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+ /* Set core clock into 500Mhz */
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+ core_write(priv, CORE_GSWPLL_GRP2,
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+ RG_GSWPLL_POSDIV_500M(1) |
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+ RG_GSWPLL_FBKDIV_500M(25));
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+
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+ /* Enable PLL */
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+ core_write(priv, CORE_GSWPLL_GRP1,
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+ RG_GSWPLL_EN_PRE |
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+ RG_GSWPLL_POSDIV_200M(2) |
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+ RG_GSWPLL_FBKDIV_200M(32));
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+
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+ /* Enable MT7530 core clock */
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+ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
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/* Setup the MT7530 TRGMII Tx Clock */
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core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
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