d1d2c0b557
Refreshed patches. Run tested: qemu-x86-64 Build tested: x86/64, imx6, sunxi/a53, layerscape/armv7+armv8_64b Signed-off-by: Petr Štetiar <ynezz@true.cz>
93 lines
2.5 KiB
Diff
93 lines
2.5 KiB
Diff
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -2201,6 +2201,31 @@ static int mtk_start_dma(struct mtk_eth
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return 0;
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}
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+static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
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+{
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+ int i;
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+
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
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+ return;
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+
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+ for (i = 0; i < MTK_MAC_COUNT; i++) {
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+ u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
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+
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+ /* default setup the forward port to send frame to PDMA */
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+ val &= ~0xffff;
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+
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+ /* Enable RX checksum */
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+ val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
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+
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+ val |= config;
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+
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+ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
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+ }
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+ /* Reset and enable PSE */
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+ mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
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+ mtk_w32(eth, 0, MTK_RST_GL);
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+}
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+
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static int mtk_open(struct net_device *dev)
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{
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struct mtk_mac *mac = netdev_priv(dev);
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@@ -2221,6 +2246,8 @@ static int mtk_open(struct net_device *d
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if (err)
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return err;
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+ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
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+
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napi_enable(ð->tx_napi);
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napi_enable(ð->rx_napi);
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mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
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@@ -2276,6 +2303,8 @@ static int mtk_stop(struct net_device *d
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if (!refcount_dec_and_test(ð->dma_refcnt))
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return 0;
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+ mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
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+
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mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
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mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
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napi_disable(ð->tx_napi);
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@@ -2402,8 +2431,6 @@ static int mtk_hw_init(struct mtk_eth *e
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mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
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mtk_tx_irq_disable(eth, ~0);
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mtk_rx_irq_disable(eth, ~0);
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- mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
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- mtk_w32(eth, 0, MTK_RST_GL);
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/* FE int grouping */
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mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
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@@ -2412,19 +2439,6 @@ static int mtk_hw_init(struct mtk_eth *e
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mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
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mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
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- for (i = 0; i < MTK_MAC_COUNT; i++) {
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- u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
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-
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- /* setup the forward port to send frame to PDMA */
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- val &= ~0xffff;
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-
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- /* Enable RX checksum */
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- val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
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-
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- /* setup the mac dma */
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- mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
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- }
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-
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return 0;
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err_disable_pm:
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -84,6 +84,8 @@
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#define MTK_GDMA_ICS_EN BIT(22)
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#define MTK_GDMA_TCS_EN BIT(21)
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#define MTK_GDMA_UCS_EN BIT(20)
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+#define MTK_GDMA_TO_PDMA 0x0
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+#define MTK_GDMA_DROP_ALL 0x7777
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/* Unicast Filter MAC Address Register - Low */
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#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
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