63066d3006
Reworked: - 0034 patchset update Added: - 080 Add support for pinctrl-msm framework Removed: - 0074-ipq806x-usb-Control-USB-master-reset.patch (we now have a dedicated driver for qcom usb) - 0047-mtd-nand-Create-a-BBT-flag-to-access-bad-block-marke (merged upstream) - 310-msm-adhoc-bus-support (it looks like it was never actually used in any dts) Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> [commit subject and description facelift, SoB fix] Signed-off-by: Petr Štetiar <ynezz@true.cz>
237 lines
5.9 KiB
Diff
237 lines
5.9 KiB
Diff
From 72ad7207954dd622a662ba884dc6c30a820123f2 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Tue, 14 Aug 2018 17:42:24 +0530
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Subject: [PATCH 05/12] clk: qcom: Add MSM8960/APQ8064's HFPLLs
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Describe the HFPLLs present on MSM8960 and APQ8064 devices.
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Acked-by: Rob Herring <robh@kernel.org> (bindings)
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Tested-by: Craig Tatlor <ctatlor97@gmail.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/qcom/gcc-msm8960.c | 172 +++++++++++++++++++
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include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
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2 files changed, 174 insertions(+)
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--- a/drivers/clk/qcom/gcc-msm8960.c
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+++ b/drivers/clk/qcom/gcc-msm8960.c
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@@ -30,6 +30,7 @@
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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+#include "clk-hfpll.h"
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#include "reset.h"
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static struct clk_pll pll3 = {
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@@ -86,6 +87,164 @@ static struct clk_regmap pll8_vote = {
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},
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};
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+static struct hfpll_data hfpll0_data = {
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+ .mode_reg = 0x3200,
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+ .l_reg = 0x3208,
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+ .m_reg = 0x320c,
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+ .n_reg = 0x3210,
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+ .config_reg = 0x3204,
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+ .status_reg = 0x321c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3214,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll0 = {
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+ .d = &hfpll0_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll0",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
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+};
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+
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+static struct hfpll_data hfpll1_8064_data = {
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+ .mode_reg = 0x3240,
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+ .l_reg = 0x3248,
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+ .m_reg = 0x324c,
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+ .n_reg = 0x3250,
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+ .config_reg = 0x3244,
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+ .status_reg = 0x325c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3254,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct hfpll_data hfpll1_data = {
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+ .mode_reg = 0x3300,
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+ .l_reg = 0x3308,
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+ .m_reg = 0x330c,
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+ .n_reg = 0x3310,
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+ .config_reg = 0x3304,
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+ .status_reg = 0x331c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3314,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll1 = {
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+ .d = &hfpll1_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll1",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
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+};
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+
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+static struct hfpll_data hfpll2_data = {
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+ .mode_reg = 0x3280,
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+ .l_reg = 0x3288,
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+ .m_reg = 0x328c,
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+ .n_reg = 0x3290,
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+ .config_reg = 0x3284,
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+ .status_reg = 0x329c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3294,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll2 = {
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+ .d = &hfpll2_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll2",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
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+};
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+
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+static struct hfpll_data hfpll3_data = {
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+ .mode_reg = 0x32c0,
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+ .l_reg = 0x32c8,
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+ .m_reg = 0x32cc,
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+ .n_reg = 0x32d0,
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+ .config_reg = 0x32c4,
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+ .status_reg = 0x32dc,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x32d4,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll3 = {
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+ .d = &hfpll3_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll3",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
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+};
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+
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+static struct hfpll_data hfpll_l2_8064_data = {
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+ .mode_reg = 0x3300,
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+ .l_reg = 0x3308,
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+ .m_reg = 0x330c,
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+ .n_reg = 0x3310,
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+ .config_reg = 0x3304,
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+ .status_reg = 0x331c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3314,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct hfpll_data hfpll_l2_data = {
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+ .mode_reg = 0x3400,
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+ .l_reg = 0x3408,
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+ .m_reg = 0x340c,
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+ .n_reg = 0x3410,
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+ .config_reg = 0x3404,
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+ .status_reg = 0x341c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3414,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll_l2 = {
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+ .d = &hfpll_l2_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll_l2",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
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+};
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+
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static struct clk_pll pll14 = {
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.l_reg = 0x31c4,
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.m_reg = 0x31c8,
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@@ -3107,6 +3266,9 @@ static struct clk_regmap *gcc_msm8960_cl
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[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
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[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
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[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
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+ [PLL9] = &hfpll0.clkr,
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+ [PLL10] = &hfpll1.clkr,
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+ [PLL12] = &hfpll_l2.clkr,
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};
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static const struct qcom_reset_map gcc_msm8960_resets[] = {
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@@ -3318,6 +3480,11 @@ static struct clk_regmap *gcc_apq8064_cl
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[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
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[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
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[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
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+ [PLL9] = &hfpll0.clkr,
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+ [PLL10] = &hfpll1.clkr,
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+ [PLL12] = &hfpll_l2.clkr,
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+ [PLL16] = &hfpll2.clkr,
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+ [PLL17] = &hfpll3.clkr,
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};
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static const struct qcom_reset_map gcc_apq8064_resets[] = {
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@@ -3477,6 +3644,11 @@ static int gcc_msm8960_probe(struct plat
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if (ret)
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return ret;
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+ if (match->data == &gcc_apq8064_desc) {
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+ hfpll1.d = &hfpll1_8064_data;
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+ hfpll_l2.d = &hfpll_l2_8064_data;
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+ }
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+
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tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
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NULL, 0);
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if (IS_ERR(tsens))
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--- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
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+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
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@@ -319,5 +319,7 @@
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#define CE3_SRC 303
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#define CE3_CORE_CLK 304
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#define CE3_H_CLK 305
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+#define PLL16 306
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+#define PLL17 307
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#endif
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