196f3d586f
5.4.102 backported a lot of stuff that our WireGuard backport already did, in addition to other patches we had, so those patches were removed from that part of the series. In the process other patches were refreshed or reworked to account for upstream changes. This commit involved `update_kernel.sh -v -u 5.4`. Cc: John Audia <graysky@archlinux.us> Cc: David Bauer <mail@david-bauer.net> Cc: Petr Štetiar <ynezz@true.cz> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
109 lines
2.8 KiB
Diff
109 lines
2.8 KiB
Diff
From: Felix Fietkau <nbd@nbd.name>
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Date: Fri, 4 Sep 2020 18:42:42 +0200
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Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
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It improves performance by eliminating the need for a cache flush for DMA on
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attached devices
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -805,6 +805,8 @@
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reg = <0 0x1a143000 0 0x1000>;
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reg-names = "port0";
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mediatek,pcie-cfg = <&pciecfg>;
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+ mediatek,hifsys = <&hifsys>;
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+ mediatek,cci-control = <&cci_control2>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
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@@ -822,6 +824,7 @@
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
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status = "disabled";
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+ dma-coherent;
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slot0: pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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@@ -848,6 +851,8 @@
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reg = <0 0x1a145000 0 0x1000>;
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reg-names = "port1";
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mediatek,pcie-cfg = <&pciecfg>;
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+ mediatek,hifsys = <&hifsys>;
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+ mediatek,cci-control = <&cci_control2>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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@@ -866,6 +871,7 @@
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
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status = "disabled";
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+ dma-coherent;
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slot1: pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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@@ -925,6 +931,11 @@
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};
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};
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+ hifsys: syscon@1af00000 {
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+ compatible = "mediatek,mt7622-hifsys", "syscon";
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+ reg = <0 0x1af00000 0 0x70>;
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+ };
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+
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt7622-ethsys",
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"syscon";
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--- a/drivers/pci/controller/pcie-mediatek.c
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+++ b/drivers/pci/controller/pcie-mediatek.c
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@@ -20,6 +20,7 @@
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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+#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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@@ -139,6 +140,11 @@
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#define PCIE_LINK_STATUS_V2 0x804
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#define PCIE_PORT_LINKUP_V2 BIT(10)
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+/* DMA channel mapping */
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+#define HIFSYS_DMA_AG_MAP 0x008
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+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0)
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+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1)
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+
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struct mtk_pcie_port;
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/**
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@@ -1068,6 +1074,27 @@ static int mtk_pcie_setup(struct mtk_pci
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}
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}
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+ if (of_dma_is_coherent(node)) {
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+ struct regmap *con;
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+ u32 mask;
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+
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+ con = syscon_regmap_lookup_by_phandle(node,
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+ "mediatek,cci-control");
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+ /* enable CPU/bus coherency */
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+ if (!IS_ERR(con))
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+ regmap_write(con, 0, 3);
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+
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+ con = syscon_regmap_lookup_by_phandle(node,
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+ "mediatek,hifsys");
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+ if (IS_ERR(con)) {
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+ dev_err(dev, "missing hifsys node\n");
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+ return PTR_ERR(con);
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+ }
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+
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+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
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+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
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+ }
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+
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for_each_available_child_of_node(node, child) {
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int slot;
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