2bbd43d065
backport upstream changes to 3.10: - 0060-flexcan.patch: - add flexcan pinctrl and devicetree config - 0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch - fix a clock issue - 0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch - fix a clock issue Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 39033
93 lines
2.1 KiB
Diff
93 lines
2.1 KiB
Diff
--- a/arch/arm/boot/dts/imx6q.dtsi
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+++ b/arch/arm/boot/dts/imx6q.dtsi
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@@ -163,6 +163,31 @@
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};
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};
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+ flexcan1 {
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+ pinctrl_flexcan1_1: flexcan1grp-1 {
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+ fsl,pins = <
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+ MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
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+ MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
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+ >;
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+ };
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+
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+ pinctrl_flexcan1_2: flexcan1grp-2 {
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+ fsl,pins = <
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+ MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
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+ MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
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+ >;
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+ };
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+ };
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+
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+ flexcan2 {
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+ pinctrl_flexcan2_1: flexcan2grp-1 {
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+ fsl,pins = <
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+ MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
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+ MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
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+ >;
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+ };
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+ };
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+
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gpmi-nand {
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <
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--- a/arch/arm/boot/dts/imx6qdl.dtsi
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+++ b/arch/arm/boot/dts/imx6qdl.dtsi
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@@ -292,13 +292,21 @@
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};
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can1: flexcan@02090000 {
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+ compatible = "fsl,imx6q-flexcan";
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reg = <0x02090000 0x4000>;
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interrupts = <0 110 0x04>;
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+ clocks = <&clks 108>, <&clks 109>;
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+ clock-names = "ipg", "per";
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+ status = "disabled";
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};
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can2: flexcan@02094000 {
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+ compatible = "fsl,imx6q-flexcan";
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reg = <0x02094000 0x4000>;
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interrupts = <0 111 0x04>;
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+ clocks = <&clks 110>, <&clks 111>;
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+ clock-names = "ipg", "per";
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+ status = "disabled";
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};
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gpt: gpt@02098000 {
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--- a/arch/arm/boot/dts/imx6dl.dtsi
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+++ b/arch/arm/boot/dts/imx6dl.dtsi
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@@ -80,6 +80,31 @@
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};
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};
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+ flexcan1 {
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+ pinctrl_flexcan1_1: flexcan1grp-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
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+ MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
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+ >;
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+ };
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+
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+ pinctrl_flexcan1_2: flexcan1grp-2 {
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+ fsl,pins = <
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+ MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
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+ MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
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+ >;
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+ };
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+ };
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+
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+ flexcan2 {
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+ pinctrl_flexcan2_1: flexcan2grp-1 {
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+ fsl,pins = <
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+ MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
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+ MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
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+ >;
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+ };
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+ };
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+
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uart1 {
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pinctrl_uart1_1: uart1grp-1 {
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fsl,pins = <
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