33 lines
835 B
Diff
33 lines
835 B
Diff
--- a/gcc/config/avr32/avr32.c
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+++ b/gcc/config/avr32/avr32.c
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@@ -6726,7 +6726,28 @@ avr32_reorg_optimization (void)
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}
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}
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- if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0)))
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+ /* Disabled this optimization since it has a bug */
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+ /* In the case where the data instruction the shifted insn gets folded
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+ * into is a branch destination, this breaks, i.e.
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+ *
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+ * add r8, r10, r8 << 2
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+ * 1:
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+ * ld.w r11, r8[0]
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+ * ...
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+ * mov r8, sp
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+ * rjmp 1b
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+ *
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+ * gets folded to:
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+ *
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+ * 1:
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+ * ld.w r11, r10[r8 << 2]
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+ * ...
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+ * mov r8, sp
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+ * rjmp 1b
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+ *
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+ * which is clearly wrong..
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+ */
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+ if (0 && TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0)))
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{
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/* Scan through all insns looking for shifted add operations */
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