196 lines
5.1 KiB
Diff
196 lines
5.1 KiB
Diff
From a7c55f5e927b69bb30912fe1c3e5bcd8751e8381 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 14 Mar 2012 15:37:19 +0100
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Subject: [PATCH 51/70] MIPS: adds gptu driver
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---
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arch/mips/lantiq/xway/gptu.c | 176 ++++++++++++++++++++++++++++++++++++++++++
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1 files changed, 176 insertions(+), 0 deletions(-)
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create mode 100644 arch/mips/lantiq/xway/gptu.c
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diff --git a/arch/mips/lantiq/xway/gptu.c b/arch/mips/lantiq/xway/gptu.c
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new file mode 100644
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index 0000000..ac82c37
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/gptu.c
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@@ -0,0 +1,176 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/ioport.h>
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+#include <linux/pm.h>
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+#include <linux/export.h>
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+#include <linux/delay.h>
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+#include <linux/interrupt.h>
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+#include <asm/reboot.h>
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+
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+#include <lantiq_soc.h>
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+#include "../clk.h"
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+
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+#include "../devices.h"
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+
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+#define ltq_gptu_w32(x, y) ltq_w32((x), ltq_gptu_membase + (y))
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+#define ltq_gptu_r32(x) ltq_r32(ltq_gptu_membase + (x))
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+
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+
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+/* the magic ID byte of the core */
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+#define GPTU_MAGIC 0x59
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+/* clock control register */
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+#define GPTU_CLC 0x00
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+/* id register */
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+#define GPTU_ID 0x08
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+/* interrupt node enable */
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+#define GPTU_IRNEN 0xf4
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+/* interrupt control register */
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+#define GPTU_IRCR 0xf8
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+/* interrupt capture register */
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+#define GPTU_IRNCR 0xfc
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+/* there are 3 identical blocks of 2 timers. calculate register offsets */
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+#define GPTU_SHIFT(x) (x % 2 ? 4 : 0)
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+#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10)
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+/* timer control register */
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+#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00)
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+/* timer auto reload register */
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+#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08)
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+/* timer manual reload register */
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+#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10)
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+/* timer count register */
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+#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18)
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+
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+/* GPTU_CON(x) */
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+#define CON_CNT BIT(2)
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+#define CON_EDGE_FALL BIT(7)
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+#define CON_SYNC BIT(8)
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+#define CON_CLK_INT BIT(10)
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+
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+/* GPTU_RUN(x) */
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+#define RUN_SEN BIT(0)
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+#define RUN_RL BIT(2)
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+
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+/* set clock to runmode */
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+#define CLC_RMC BIT(8)
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+/* bring core out of suspend */
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+#define CLC_SUSPEND BIT(4)
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+/* the disable bit */
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+#define CLC_DISABLE BIT(0)
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+
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+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
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+
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+enum gptu_timer {
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+ TIMER1A = 0,
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+ TIMER1B,
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+ TIMER2A,
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+ TIMER2B,
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+ TIMER3A,
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+ TIMER3B
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+};
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+
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+static struct resource ltq_gptu_resource =
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+ MEM_RES("GPTU", LTQ_GPTU_BASE_ADDR, LTQ_GPTU_SIZE);
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+
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+static void __iomem *ltq_gptu_membase;
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+
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+static irqreturn_t timer_irq_handler(int irq, void *priv)
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+{
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+ int timer = irq - TIMER_INTERRUPT;
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+ ltq_gptu_w32(1 << timer, GPTU_IRNCR);
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+ return IRQ_HANDLED;
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+}
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+
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+static void gptu_hwinit(void)
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+{
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+ struct clk *clk = clk_get_sys("ltq_gptu", NULL);
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+ clk_enable(clk);
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+ ltq_gptu_w32(0x00, GPTU_IRNEN);
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+ ltq_gptu_w32(0xff, GPTU_IRNCR);
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+ ltq_gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);
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+}
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+
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+static void gptu_hwexit(void)
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+{
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+ ltq_gptu_w32(0x00, GPTU_IRNEN);
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+ ltq_gptu_w32(0xff, GPTU_IRNCR);
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+ ltq_gptu_w32(CLC_DISABLE, GPTU_CLC);
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+}
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+
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+static int ltq_gptu_enable(struct clk *clk)
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+{
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+ int ret = request_irq(TIMER_INTERRUPT + clk->bits, timer_irq_handler,
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+ IRQF_TIMER, "timer", NULL);
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+ if (ret) {
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+ pr_err("gptu: failed to request irq\n");
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+ return ret;
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+ }
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+
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+ ltq_gptu_w32(CON_CNT | CON_EDGE_FALL | CON_SYNC | CON_CLK_INT,
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+ GPTU_CON(clk->bits));
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+ ltq_gptu_w32(1, GPTU_RLD(clk->bits));
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+ ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) | clk->bits, GPTU_IRNEN);
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+ ltq_gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
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+ return 0;
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+}
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+
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+static void ltq_gptu_disable(struct clk *clk)
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+{
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+ ltq_gptu_w32(0, GPTU_RUN(clk->bits));
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+ ltq_gptu_w32(0, GPTU_CON(clk->bits));
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+ ltq_gptu_w32(0, GPTU_RLD(clk->bits));
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+ ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) & ~clk->bits, GPTU_IRNEN);
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+ free_irq(TIMER_INTERRUPT + clk->bits, NULL);
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+}
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+
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+static inline void clkdev_add_gptu(const char *con, unsigned int timer)
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+{
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+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
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+
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+ clk->cl.dev_id = "ltq_gptu";
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+ clk->cl.con_id = con;
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+ clk->cl.clk = clk;
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+ clk->enable = ltq_gptu_enable;
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+ clk->disable = ltq_gptu_disable;
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+ clk->bits = timer;
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+ clkdev_add(&clk->cl);
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+}
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+
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+static int __init gptu_setup(void)
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+{
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+ /* remap gptu register range */
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+ ltq_gptu_membase = ltq_remap_resource(<q_gptu_resource);
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+ if (!ltq_gptu_membase)
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+ panic("Failed to remap gptu memory");
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+
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+ /* power up the core */
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+ gptu_hwinit();
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+
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+ /* the gptu has a ID register */
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+ if (((ltq_gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) {
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+ pr_err("gptu: failed to find magic\n");
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+ gptu_hwexit();
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+ return -ENAVAIL;
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+ }
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+
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+ /* register the clocks */
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+ clkdev_add_gptu("timer1a", TIMER1A);
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+ clkdev_add_gptu("timer1b", TIMER1B);
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+ clkdev_add_gptu("timer2a", TIMER2A);
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+ clkdev_add_gptu("timer2b", TIMER2B);
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+ clkdev_add_gptu("timer3a", TIMER3A);
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+ clkdev_add_gptu("timer3b", TIMER3B);
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+
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+ pr_info("gptu: 6 timers loaded\n");
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+
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+ return 0;
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+}
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+
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+arch_initcall(gptu_setup);
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--
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1.7.7.1
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